Abhay Saxena ¹, Ashutosh Bhatt ², Parth Gautam ¹, Puneet Verma ³, Chandrashekhar Patel ¹

Affiliations
1 Dev Sanskriti Vishwa Vidayalaya, Haridwar, Uttarakhand-249411, IN
2 Department of Computer Science, BIAS, Bhimtal, Uttarakhand-263136, IN
3 Department of Computer Science, SIT, Pithoragarh, IN

Abstract

Green computing is making revolution by bringing high speed processor with less power consumption. Our paper is based on this philosophy. Objectives: To come out High Performance FIFO for processor by minimizing the power consumption. Methods/Statistical Analysis: To make FPGA based design of FIFO we used voltages and frequency scaling techniques. Keeping voltage constant at 2.3 volt we varied frequency from 20MHz to 250MHz and for other experiment we kept the frequency constant and varies voltages from 1volt to 2.3 volt. Findings: The power consumption is reduced to 95.79% on voltage scaling where as there is a 4.38% less power consumption on frequency scaling. Application/Improvements: It will surely help in futuristic processor development.

Keywords

Field Programmable Gate Array (FPGA), First in First Out (FIFO), Hardware Description Language (HDL), High Performance Design, Voltage Scaling.

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Abhay Saxena ¹, Chandrashekhar Patel ¹, M. Sadiq Ali Khan ²

Affiliations
1 Dev Sanskriti Vishvavidyalaya, Haridwar - 249411, Uttarakhand, IN
2 Department of Computer Science, University of Karachi, PK

Abstract

In our work we have designed CRC using the LVCMOS IO standards which are stands for Low Voltage Complementary Metal Oxide Semiconductor. In this work we have worked with four kinds of LVCMOS (LVCMOS 12, LVCMOS 15, LVCMOS 18, LVCMOS 25). For LVCMOS 12 when we scaled down the frequency form 50GHz to 10 GHz we found 64.41% reduction in total power. For LVCMOS 15 when we change down the frequency form 50GHz to 10GHz we found 67.58% reduction in total power. For LVCMOS 18 when we scaled down the frequency form 50GHz to 10 GHz we found 69.54% reduction in total power. In last when we reduced the frequency form 50GHz to 10GHz in LVCMOS 25 we found 64.41% reduction in total power. Our CRC design is implemented on Virtex-6 FPGA family.

Keywords

40 nm FPGA, CRC, Energy Efficient, Low Power, LVCMOS IO Standard.

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