S. Marlin ¹, S. D. Sundarsingh Jebaseelan ², B. Padmanabhan ¹, G. Nagarajan ¹

Affiliations
1 Sathyabama University, Chennai, IN
2 Sathyabama University, Chennai

Abstract

This work deals with power quality improvement by using FACTS devices. When the reactive power of the load is changing continuously, a suitable fast response compensator is needed. Unified Power Flow Controller and Thyristor Controller Series Capacitor are two such compensators belonging to FACTS devices which are used in this work. Models for the UPFC and TCSC are developed using MATLAB Simulink. The simulation results for thirty bus system with UPFC and TCSC are presented.

Keywords

FACTS Controller, MATLAB, Simulink, TCSC, UPFC

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B. Padmanabhan ¹, L. Premalatha ²

Affiliations
1 Department of Electrical and Electronics Engineering,Sathyabama University, Chennai - 600119, Tamil Nadu, IN
2 School of Electrical Engineering, Vellore Institute of Technology (VIT) University, Chennai - 632014, Tamil Nadu, IN

Abstract

Dynamic Power Dispatch (DPD) intends to schedule the online generators output with the forecasted load demand over a certain period of time, in order to operate an electric power system most economically within its operating limits. The behavior and the activity of honey bees during food foraging is implemented as a Honey Bees Searching Optimization (HBSO) technique in solving the DPD problem. The HBSO algorithm provides a balance between exploration and exploitation of a search space. Further, the HBSO is independent of control parameters when compared to other techniques. The DPD formulation includes ramp rate constraint, rectified sinusoidal effect, uniformity and disparity constraint, which normally present in the realistic power system. In order to express the efficacy of the HBSO algorithm a test case of 6 units DPD problem is considered and lower fuel cost is obtained when compared with other algorithm.

Keywords

Dynamic Power Dispatch, HBSO Algorithm, Power Balance Constraint, Ramp Rate Constraint, Valve Point Loading.

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B. Padmanabhan ¹

Affiliations
1 Department of Electrical and Electronics Engineering, Jeppiaar Nagar, Chennai – 600119, Tamil Nadu, IN

Abstract

This paper mainly focuses on to design a nine- level inverter for power generation using solar system to produce a nearly sine wave with reduced total harmonic distortion. The input from PV array is boosted using a dc-dc boost converter and fed into the nine-level inverter as three independent voltage sources. The capacitor selection circuit converts the three output voltage sources into a four-level dc voltage and it is further converted into nine-level ac voltage by full bridge converter. Hence the proposed system generates a sinusoidal output which is in phase with the utility voltage. The advantages of the proposed system is, it uses only nine power electronic switches, which results in reduced voltage stress and reduced total harmonic distortion without using any filter in utility side. Whereas, traditional system uses 16 power electronic switches and four independent dc voltage sources to produce a nine-level output voltage. By using minimum number of power electronic switches, the proposed system is compact and robust.

Keywords

Capacitor Selection Circuit, Nine-level AC Voltage, Nine-level Inverter, Sinusoidal Output, Total Harmonic Distortion

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