Sarita Kumari ¹, Rishab Mehra ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi - 835215, Jharkhand, IN

Abstract

Objectives: The impact of process variations on the open circuit voltage gain of CMOS inverting amplifiers is investigated and appropriate aspect ratios are calculated so as to minimize the effect of threshold voltage modulation in short channel devices. Methods/Analysis: A diode connected MOS voltage divider is used for biasing the amplifiers. These dividers are less bulky as compared to their resistive counterparts, save chip area and provide better reliability when subjected to variations. Findings: The sensitivity parameters for the voltage gain are modeled and their dependences are studied. All simulation results have been performed using CADENCE Virtuoso Analog Design Environment @ 45-nm technology node. Application: Push-pull inverting amplifiers are used in CMOS Transimpedance Amplifier forlow noise, high gain and large dynamic range. Transimpedance amplifiers find numerous applications inthe field of optical communications.

Keywords

Aspect Ratio, Gain, Inverting, MOS Divider, Saturation, Sensitivity, Variability.

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Swapnil Sourav ¹, Rishab Mehra ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi, Jharkhand – 835215, IN

Abstract

Objectives: The impact of process, voltage and temperature (PVT) variations on the voltage gain of a CMOS differential amplifier is investigated. Methods and analysis: Appropriate biasing is provided using diode-connected MOS voltage dividers. These dividers are less bulky as compared to their resistive counterparts, save chip area and provide better performance when subjected to variations. In addition, the transistors are sized suitably to minimize the effect of threshold voltage modulation in short-channel devices. Findings: The sensitivity parameters for the voltage gain are modeled and their dependences are studied. All simulation results have been performed using Virtuoso Analog Design Environment of Cadence @ 45-nm technology node. Application/ Improvement: Diode-connected MOS voltage dividers are used to bias the amplifier which provide immunity against PVT variations and hence improve system performance.

Keywords

Aspect Ratio, Differential, Gain, MOS Divider, Saturation, Sensitivity, Variability.

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Swapnil Sourav ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi, Jharkhand – 835215, IN

Abstract

Objectives: This paper carries out robustness study on p-channel and n-channel input differential amplifier (which is also known as single-stage operational transconductance amplifier). Methods and Analysis: The impact of Process, Voltage and Temperature (PVT) variations on the design metrics of both differential amplifiers is studied and suitable conclusions are drawn. Findings: The n-channel input differential amplifier is found to be more robust than p-channel input differential amplifier. Moreover, it provides higher gain, and 3-dB bandwidth as compared to its p-channel counterpart. All the results were obtained from extensive simulation using Virtuoso Analog Design Environment of Cadence @ 45-nm technology node. Application: Operational Transconductance Amplifier (OTA) can be used in the design of simple amplifiers with voltage-controllable gain and to the design of first-order and second-order active filters with controllable gains and controllable critical frequencies.

Keywords

Differential Amplifier, PVT Variation, Robustness, Single-stage OTA.

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Vikash Kumar ¹, Manish Kumar Pandey ¹, Shashank Kumar Ranu ¹, Prashant Gupta ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University),Mesra, Ranchi, Jharkhand, IN

Abstract

Objective: The aim of this work is to design a robust and reliable XOR circuit for ultra-low power operation in sub-threshold region. Method/Analysis: Comprehensive simulations have been carried out on SPICE using 16-nm predictive technology model (PTM) to accomplish our objective. Findings: A Schmitt-trigger based approach is employed to alleviate the effect of device threshold (Vt)fluctuation on XOR circuits. The proposed XOR circuit exhibits narrower spread in its design metrics proving its reliability in sub-45nm regime. Novelty/Improvement: This paper also analyzes various existing XOR gates in presence of process and environment (voltage and temperature)fluctuations to validate their performance. The proposed technique offers full voltage swing. Variability of the design metrics (propagation delay and power dissipation) is investigated and several XOR circuits are compared. The proposed Schmitt-trigger based XOR circuit exhibits narrower spread in its design metrics proving its reliability in sub-45nm regime.

Keywords

Full Voltage Swing, Propagation Delay, Power, Variability, XOR.

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Vikash Kumar ¹, Yashdeep Singh ¹, Ravi Kumar Prinshu ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University),Mesra, Ranchi – 835215, Jharkhand, IN

Abstract

Objective: As the need for energy increases, new technologies should replace the conventional energy resources. Energy harvesting is one of these technologies and finds applications in many areas such as wireless sensor networks, biomedical applications. Findings: This paper presents a low-voltage charge pump which works at input voltage as small as 100 mV and is suitable for wireless energy harvesting applications. With 100 mV input, the proposed charge pump provides an output of 1.05 V. This output voltage is adequate for charging low power devices for biomedical applications and wireless sensor networks. Novelty/Improvement: The proposed charge pump has the voltage conversion ratio (M) greater than 10 and the circuit does not need any start-up voltage mechanisms for the operations. Method/Analysis: The result presented in this work is based on extensive simulation on SPICE and are experimentally validated CNFET model of Stanford University.

Keywords

Charge Pump, Clock Generator, CNFET, Energy Harvesting.

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Vikash Kumar ¹, Prashant Gupta ¹, Shashank Kumar Ranu ¹, Manish Kumar Pandey ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi – 835215, Jharkhand, IN

Abstract

Objective: The objective of this paper is to realize an n-bit reversible number generator. Several designs of number generator and their corresponding constraints with feedback controller and initial state have also been discussed. Method/Analysis: The proposed design is validated by simulating the results in Verilog HDL. Findings: In this paper a design is presented to implement an n bit number generator as a finite state automation, using reversible logic for the implementation of the transition network. A realizable circuit is designed to implement the n-bit number generator using feedback controllers. Novelty/Improvement: With the use of reversible logic, the designed circuit reaches all the possible states and consumes no power.

Keywords

Finite State Automation, Number Generator, Reversible Computing, Reversible Logic Synthesis.

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Soumitra Pal ¹, Aminul Islam ¹

Affiliations
1 Birla Institute of Technology, Mesra, Ranchi - 835215, Jharkhand, IN

Abstract

Objectives: The objective of this paper is to design a threshold voltage (Vt) variation tolerant low leakage low power SRAM cell. Methods/Analysis: The proposed cell has the same architecture as that of read decoupled 7T SRAM cell (RD7T) with an exception of TG instead of access NMOS transistors. This cell is operated in super-threshold region at power supply varying from 0.62V to 0.77V. Findings: Various design metrics of the proposed cell are estimated and compared with RD7T. The proposed cell offers robustness against the process induced variations by providing a 1.1 × narrower spread in read time (TRA) distribution at a cost of 1.23 × penalty in TRA. It also provides 2.06 × narrower spread in read current (IREAD) distribution at the price of 1.13 × penalty in IREAD. It offers 1.42 × lower leakage current and also a 1.06 × lower hold power as compared to that of RD7T. Moreover, it also provides 1.13 × narrower spread in hold power with same read static noise margin (185 mV). Novelty /Improvement: The Monte Carlo based comparative analysis proves that the suggested cell is tolerant to the Vt fluctuations to a great extent.

Keywords

Leakage Current, Leakage Power Dissipation, Read Current, Read Delay, RSNM, Transmission Gate, WSNM.

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Chandramauleshwar Roy ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi - 835215, Jharkhand, IN

Abstract

Objective: In this article an SRAM cell based on Column Line Assist (CLA) and DTMOS techniques is proposed. Method/Analysis: The CLA scheme is used to provide a dual path during read and write. The availability of an extra path causes read and write delay to be lesser in case of the proposed design when compared to the conventional 10T SRAM cell. Findings: The use of DTMOS scheme causes the threshold voltage of the MOSFETs to be lower, thereby providing faster switching. Our proposed design is compared to the previously designed conventional 10T SRAM cell (CON 10T). It is found that the proposed design shows 1.91 × increments in read current and 43.3% narrower spread in read current. In terms of read delay, an improvement of 1.68 × is observed. Also, the variability is improved by 70%. The read static noise margin (RSNM) of the proposed design is 0.85 × lesser as compared to the CON10T cell. Novelty/Improvement: The write current and write static noise margin increase by 6.2% and 3 × at VDD= 0.4V.

Keywords

DTMOS and CLA Techniques, Hold Power, Read Delay, Read Current (IREAD), RSNM, Write Delay, WSNM.

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Manisha Guduri ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi - 835215, Jharkhand, IN

Abstract

Objectives: This paper analyses various Complementary MOS (CMOS) based XOR circuits in terms of their output voltage levels at deep subthreshold/low frequency region at 16-nm technology node and finds out the suitable XOR circuit for ultralow-power applications. Methods/Analysis: It also provides the worst case high and low output level for various XOR circuits at supply voltage 130 mV. Findings: In addition, it compares the average power dissipation that is the sum of both dynamic and leakage power dissipation (stand-by power dissipation) of XOR circuits along with the variability analysis of power dissipation in order to find the XOR circuit which is most robust and dissipate the least average power. Novelty/Improvement: Simulation result shows that Power-less XOR circuit is having a good output high and low level in all cases and most promising in terms of robustness and average power dissipation among all the other XOR circuits at deep subthreshold/ low frequency region of operation.

Keywords

Average Power Dissipation, CMOS, Low Frequency, Subthreshold Region.

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Shrey Khanna ¹, Debosmit Majumder ¹, Vikash Kumar ¹, Santashraya Prasad ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi - 835215, Jharkhand, IN

Abstract

Objective: This paper proposes an electronically tunable active grounded inductor circuit using VDVTA as a new active element. The circuit can replace spiral passive inductors for all Analog Signal Processing and data communications operations. Method/Analysis: The impact of temperature variation on its resonant frequency is investigated using Virtuoso Analog Design Environment of Cadence @ 45-nm CMOS technology node. Findings: This paper carries out a study on CMOS realization of Voltage Differencing Voltage Transconductance Amplifier (VDVTA) and its application as an active grounded inductor. A Bandpass filter circuit is realized using the VDVTA based grounded inductor. Furthermore, the impact of temperature variation on the response of the bandpass filter is analyzed and presented. Novelty/Improvement: The proposed circuit uses only active elements and a grounded capacitor. Due to this, the circuit finds applications in all canonical operations and integrated circuit implementations.

Keywords

Active Inductor, Bandpass Filter, Volatge Differencing Voltage Transconductance Amplifier (VDVTA)

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Chandramauleswar Roy ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi - 835215, Jharkhand, IN

Abstract

Objective: This article presents a transmission gate based novel 2T2M RRAM using memristor as memory element. Method/Analysis: Simulation results of critical design metrics of proposed 2T2M RRAM cell and conventional SRAM cell are compared. Findings: The proposed 2T2M RRAM cell achieves 1.35 × lower read delays at the expense of 1.02 ×higher write delay than conventional 6T SRAM cell at nominal V_dd. Moreover, being non-volatile it is more power efficient and also saves at least 50% of area. Novelty/Improvement: It is more power efficient and saves 50% of area. Further, being differential in nature, proposed cell is more immune to PVT variation during read operation.

Keywords

Memristor, Nonvolatile, RRAM, Read Delay, Transmission Gate, Write Delay

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Manisha Guduri ¹, Amit Krishna Dwivedi ¹, Aminul Islam ¹

Affiliations
1 Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi - 835215, Jharkhand, IN

Abstract

Objectives: The objective of this research paper is to design High Vt-Low Leakage FDSOI Device for Ultra-Low Power Operation. Methods/Analysis: This research work presents the modeling of fully depleted silicon on insulator (FDSOI) device with 350-nm gate length. This paper investigates threshold voltage (Vt) and leakage power of the different FDSOI devices in order to design high threshold voltage and low leakage device. Findings: It is observed that device5 shows higher Vt and dissipates lower leakage power when compared to that of other devices (devices1−4). The threshold voltage and subthreshold slope (SS) of device5 are observed to be 0.199 V (~0.2 V) and 80 mV/decade respectively. The leakage power of the device at drain voltage of 1 V is 41.9 nW. Novelty /Improvement: This kind of FDSOI device is a platform for designing circuits at nano scale regime for ultra-low power applications.

Keywords

FDSOI Device, Leakage Power, Threshold Voltage, Subthreshold Slope

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