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Moyal, Vishal
- Static and Dynamic Parameter Estimation of Stacked CMOS Inverter based TIQ for Flash ADC
Authors
Source
Programmable Device Circuits and Systems, Vol 8, No 7 (2016), Pagination: 191-194Abstract
This paper aims to estimate parameters of a 3-bit Flash Analog to Digital Converter (ADC) using Threshold Inverter Quantizer (TIQ) technique implemented with stacked CMOS Inverter. The stacked TIQ based flash ADC requires 2n-1 comparators like conventional ADCs. Though, each comparator in the TIQ flash ADC has different sizes to cater internal reference voltages, which is achieved by systematically varying widths of PMOS and NMOS transistors of TIQ inverter, as a result 70% reduction of power consumption is achieved. The static and dynamic parameter are evaluated for the implemented design and obtained result as follows DNL = ± 0.23 LSB, INL = ± 0.15 LSB, SNR= 17.38 dB, SFDR = 21.98 dB and ENOB = 2.5 bits. The design consumes 5.98 µW power when simulated at 1 KHz, 1.2Vpp input signal at Vdd = 1.2V dc with load capacitance of 1fF.
Keywords
ADC, TIQ, CMOS, PMOS, NMOS, VTC, MUX, LSB, DNL, INL, SNR, SFDR, ENOB.
- Parametric Analysis of DFAL Based Dynamic Comparator
Authors
1 Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Technical Campus, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 1 (2017), Pagination: 354-358Abstract
In Complementary Metal Oxide Semiconductor (CMOS) technology, the advancement in manufacturing of semiconductor processing has changed the designing challenges for the researchers. The challenges that are now being vital are high speed and low power computing devices. This paper presents a novel dynamic comparator with DFAL (Diode Free Adiabatic Logic) inverter that employs the principle of adiabatic logic. As compared to the conventional CMOS technique, the adiabatic logic technique shows more promising results. The proposed Dynamic Comparator, not only provides low power consumption and reduces the delay, but also improves the energy efficiency in comparison to the conventional Dynamic Comparator. The design has been simulated using Cadence Virtuoso Spectre simulator in gdpk 90nm Technology.Keywords
Conventional Dynamic Comparator, Adiabatic Logic, DFAL Inverter, Low Power.References
- V. Deepika and Sangeeta Singh, “Design and Implementation of A Low Power, High Speed Comparator”, Procedia Materials Science, Vol. 10, pp. 314-322, 2015.
- Jun He, Sanyi Zhan, Degang Chen and Randall L. Geiger, “Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 56, No. 5, pp. 911-919, 2009.
- Islam T. Abougindia, Ismail Cevik, Fadi N. Zghoul and Suat U. Ay, “A Precision Comparator Design with A New Foreground Offset Calibration Technique”, Analog Integrated Circuits and Signal Processing, Vol. 83, No. 2, pp. 243-255, 2015.
- Takayuki Okazawa, Ippei Akita and Makoya Ishida, “A Digitally Calibrated Dynamic Comparator using Time-Domain Offset Detection”, Analog Integrated Circuits and Signal Processing, Vol. 81, No. 3, pp. 561-570, 2014.
- Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa, “A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs”, Proceedings of IEEE Asian Solid-State Circuits Conference, pp. 269-272, 2008.
- N.H.E. Weste and D. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, 3rd Edition, Pearson Education, 2011.
- Philip Teichmann, “Fundamentals of Adiabatic Logic”, Adiabatic Logic, Vol. 34, pp. 5-22, 2012.
- Irfan Ahmad Pindoo, Tejinder Singh, Amritpal Singh, Ankit Chaudhary and P. Mohan Kumar, “Power Dissipation Reduction Using Adiabatic Logic Techniques for CMOS Inverter Circuit”, Proceedings of IEEE 6th International Conference on Computing, Communication and Networking Technologies, pp. 1-6, 2015.
- Yong Moon and Deog Kyoon Jeong, “An Efficient Charge Recovery Logic Circuit”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, pp. 514-522, 1996.
- Yibin Ye and Kaushik Roy, “QSERL: Quasi-Static Energy Recovery Logic”, IEEE Journal of Solid-state Circuits, Vol. 36, No. 2, pp. 239-248, 2001.
- N. Anuar, Y. Takahashi and T. Sekine, “Two Phase Clocked Adiabatic static CMOS Logic and its Logic Family”, Journal of Semiconductor Technology and Science, Vol. 10, No. 1, pp. 1-10, 2010.
- Shipra Upadhyay, R.A. Mishra, R.K. Nagaria and S.P. Singh, “DFAL: Diode-Free Adiabatic Logic Circuits”, ISRN Electronics, Vol. 2013, pp. 1-12, 2013.
- Heena Parveen and Vishal Moyal, “Implementation of Low Power Adiabatic based Inverter for Dynamic Comparator”, International Journal of Science and Research, Vol. 6, No. 1, pp. 2320-2323, 2017.
- A Low Power Threshold Inverter Quantizer Comparator Using Diode Free Adiabatic Logic for 1.2 V, 3-Bit Flash Analog to Digital Converter
Authors
1 Department of Electronics & Telecommunication, Shri Shankaracharya Technical Campus, Shri Shankaracharya Institute of Tech. & Mgmt. Bhilai, IN
2 Shri Shankaracharya Technical Campus, Shri Shankaracharya Engineering College, Bhilai, IN
Source
Programmable Device Circuits and Systems, Vol 10, No 3 (2018), Pagination: 44-48Abstract
Diode Free Adiabatic Logic (DFAL) based Threshold Inverter Quantizer (TIQ) is recommended in this paper for implementation of a 3-bit Flash type Analog to Digital Converter. The advised work is simulated with TSMC-65nm Technology on Cadence tool. For appropriate implement of DFAL-TIQ, it is requisite to have a suitable reference voltage for each of the comparator and it is done by accurately sizing the transistors of the comparators. The average power consumed by the advised Flash type ADC when simulated at 100 Hz, 1.2Vpp and for 1fF capacitive load is 5.53 µW, which is 66.03 % lesser than that of the power consumed by Flash ADC containing conventional CMOS-TIQ comparator, and the static parameters observed as: DNL = + 0.56 LSB /-0.61 LSB and INL = +0.40 LSB /-0.43 LSB, respectively.