Informatics Publishing Limited

Richa Shukla ¹, Vandana Niranjan ¹

Affiliations
1 Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, IN

Abstract

Reversible logic is gaining importance in the context of upcoming fields such as nanotechnology, cellular automata, quantum level computation and low power VLSI design. The most attractive feature in reversible circuits is that there is one to one correspondence between input and output vectors. Therefore these circuits do not lose any information during computation. In this work we have improved the performance of reversible logic adder by modifying its structure. A delay and power efficient vedic multiplier has been implemented using proposed adder. All the circuits have been designed at 90 nm CMOS technology using Cadence Virtuoso software. Based on the results, it is concluded that the performance of a carry look ahead (CLA) adder gives best performance by changing the type of reversible gate used in its structure. The performance improvement is in terms of reduced number of gates by almost 60% reduced ancillary inputs by 46% and reduced number of garbage outputs by almost 48%. The proposed CLA adder may also find many applications in multiply and accumulate units.

Keywords

Ancillary Inputs, Carry Look Ahead Adder, Garbage Outputs, Reversible Logic, Low Power.

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Meenali Janveja ¹, Vandana Niranjan ²

Affiliations
1 Department of Electronics and Communication Engineering, G. L Bajaj Institute of Technology and Management, IN
2 Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, IN

Abstract

Multiplier is a crucial block of most of the digital arithmetic applications. With the advancement in the field of VLSI, achieving high speed and low power consumption has become a major concern for the designers. As multiplier block consumes large amount of power and has a major role to play in the speed of the circuit therefore its optimization will improve the performance of the circuit. The process of multiplication is implemented in hardware using shift and add operation, so use of efficient adder circuit will lead to improved multiplier. In this paper, reduced complexity Wallace tree multiplier circuit is proposed that uses efficient and improved adder. The circuits are designed using 90nm technology and simulated in Cadence Virtuoso. The proposed Wallace tree structure offers a decrement of approximately 70% in dissipation of power, approximately 86% in power delay product and 60% in area. The proposed multiplier is suitable to use in applications such as DSP structures, ALU's and several low power and high speed arithmetic applications.

Keywords

Wallace Tree, Full Adder, Pass Transistor Logic, Power Dissipation, Delay.

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Vandana Niranjan ¹

Affiliations
1 Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, IN

Abstract

This work presents an elegant methodology using pulsed latch instead of flip-flop without altering the existing design style. Pulsed-latch technique retain the advantages of both latches and flip-flops and thus one can achieve both high speed and lower power consumption simultaneously. In this work, pulsed latch technique has been used to reduce the delay of various shift registers without increasing any power consumption. In very high speed VLSI circuits due to heavy pipelining there is requirement of low power edge triggered flip-flops. However, for low power consumption in these very high speed VLSI circuits, the migration from flip-flop to pulsed latch technique has become a great success. In the proposed work, non-overlapped delayed pulse clock has been used in pulse latch technique to eliminate the timing problem between the pulsed latches. All the proposed shift registers have been designed in 90 nm CMOS technology and their functionality have been verified using Cadence Virtuoso. From this work, it has been concluded that, the pulse latch technique reduces the power consumption significantly in the designed registers and overall there is an improvement in power delay product. Further, it is pertinent to mention that the proposed registers require less number of transistors for their implementation as compared to conventional versions.

Keywords

Low Power, Non-Overlapped Pulse, Pulsed Latch Technique, Flip-Flop, Delay, Shift Register.

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Nimeesha ¹, Shikha Soni ¹, Vandana Niranjan ¹, Ashwni Kumar ¹

Affiliations
1 Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, IN

Abstract

This paper presents a new adaptive biasing technique for improving the slew rate of CMOS opamps without increasing the power consumption. All the proposed circuits for adaptive biasing are implemented using a current subtractor and NMOS based circuit. Further, the input stage of opamp in proposed circuits were substituted by Flipped Voltage Follower circuit and Self Cascode structure to study their effects on adaptive biasing circuits. The conclusion of this work is that there is a notable enhancement in slew rate, settling time and power dissipation in proposed adaptive biasing techniques. All the circuits have been designed using 180nm CMOS technology and simulated using cadence virtuoso.

Keywords

Adaptive Biasing, Opamp, Slew Rate, Flipped Voltage Follower, Self Cascode, Power Dissipation.

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