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Vignesh, V.
- Congestion and Stability-Aware Multipath Routing Protocol in Manets
Authors
1 Department of Information Technology, Sri Ramakrishna Engineering College, Coimbatore, TN, IN
Source
Indian Journal of Innovations and Developments, Vol 3, No 4 (2014), Pagination: 68-73Abstract
Objectives: In mobile ad hoc networks (MANETs), congestion is a main factor while packets transmitted from the source to the destination. The high packet loss, high delay and waste of resource utilization time are occurring due to the congestion. By using the average queue length, the CSAMR (Congestion and Stability-aware Multipath Routing) detects the present congestion level and packets are transmitted through congestion free path.
Methods: Congestion aware technique is introduced for detecting the congestion along the routing path. In this method, the average queue length at the node level is computed based on the estimations. Here the node detects the present congestion stage and sends a warning information message to its neighboring nodes. Finally the packets are transmitting from source to destination along with congestion free path.
Results: The proposed method achieves high performance in terms of packet delivery ratio and end-to-end delay.
Conclusion: The congestion aware method is used to reduce the delay and buffer overflow caused by network congestion and hence it facilitates the network to perform better. In this method, dynamic congestion aware routing method is used for detects the congestion level according to the estimations of the average queue length.
Keywords
Mobile Ad Hoc Networks, Congestion, Queue Length, Node Disjoint, Packet Transmission.- Implementation of 8 Bit Ripple Carry Adder and Serial Adder Using Clocked Adiabatic Logic
Authors
1 VIT University, Vellore, Tamilnadu, IN
2 School of Electronics, Vellore Institute of Technology, University Vellore, Tamilnadu, IN
Source
Digital Signal Processing, Vol 3, No 7 (2011), Pagination: 371-375Abstract
This paper presents the design of adders using the ultra low power two phase clocked adiabatic logic. Using this logic the basic NAND, NOR, EXOR is designed for designing the 8bit ripple carry adder and the D-flip-flop is constructed using the adiabatic NAND logic and the shift register is evaluated using the D flip-flop to design the serial adder and the performance parameters such as energy dissipation, frequency of operation, are compared with static CMOS and from the results found that it saves up to 70% of power.- GSM Based Atomized Toll Gate System Using Passive RFID
Authors
1 Department Of Electronics and Communication Engineering, Dr.N.G.P Institute of Technology, Coimbatore, IN
Source
Automation and Autonomous Systems, Vol 5, No 5 (2013), Pagination: 215-217Abstract
GSM Based Atomized Toll Gate System Using Passive Radio Frequency Identification emerges as a converging technology where time and efficiency are the matter of priority in toll collection systems of present day. In order to overcome the major issue of collision, in our project the reader is placed in a strip which is laid beneath the lane, and the tag is placed in the front side of the number plate. The object detection sensor which is placed on the side of the road detects the approach of the oncoming vehicle and intimates the stepper motor to raise the strip. Thus the reader raises to ground level and reads the information in the tag and the transaction takes place through a centralized database and the aftermath details of the transaction is intimated to the user’s mobile through GSM technology.Keywords
Radio Frequency Identification, Global System for Mobile Communication.- Simulation and Analysis of RSSI Based Trilateration Algorithm for Localization in Contiki-OS
Authors
1 Department of Electrical and Electronics Engineering, Manakula Vinayagar Institute of Technology, IN
2 Department of Electronics and Communication Engineering, Perunthalaivar Kamarajar Institute of Engineering and Technology, IN
3 HCL Technologies, IN
4 IGCAR, Kalpakkam, IN