Informatics Publishing Limited

K. Niranjan Reddy ¹, U. DhanaLakshmi ¹, P. V. Y. Jaya Sree ²

Affiliations
1 Malla Reddy Engineering College for Women, Hyderabad, Telangana State, IN
2 Gitam Institute of Technology, Gitam University, Visakhapatnam, AP, IN

Abstract

The OPB GPIO design provides a general purpose input/output interface to a 32-bit On-Chip Peripheral Bus (OPB). The GPIO IP core is user-programmable generalpurpose I/O controller. That is use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals. It is one of the important peripheral that is listed on any FPGA board. In this project we are atomizing the operation of the GPIO by writing the code in SYSTEM-VERILOG and simulating it in QUESTA MODELSIM. The main aim of this project is to verify the output by using GPIO pins depending up on the preference the code. We verify the GPIO modules by using UVM [Universal verification Methodology]. The functional verification of the RTL design of the GPIO is carried out for the better optimum design.

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S. Thangavel ¹, U. Dhanalakshmi ²

Affiliations
1 Department of EEE, K. S. Rangasamy College of Technology, Tiruchengode, Tamilnadu, IN
2 Department of EEE, K. S. Rangasamy College of Technology, Tiruchengode, Tamilnadu, IN

Abstract

Power system networks are becoming more interconnected and complicated. Therefore, the control centers feel the necessity of robust and scalable methods for power system state estimation that maintain performance suitably for large-scale systems. Utilities recently have been operating with less amount of money invested in transmission infrastructure and enhanced economic pressure contributing towards occurrence of blackouts. So blackout is avoided by the exact state of power system is required in order to take efficient corrective and preventive action. State estimation help in getting a good picture of system state. State estimation is a methodology that provides the best possible approximation for the state of a system by processing the available information therefore it can provide a real time data for many of the central control and dispatch functions in a power system. This paper presents a Phasor Measurement Unit (PMU) based state estimation in classic HVDC link using Weighted Least Square (WLS) algorithm. The algorithm and simulation are renowned with MATLAB software.

Keywords

Phasor Measurement Unit (PMU), State Estimation, Weighted Least Square (WLS) algorithm, High Voltage Direct Current (HVDC) Links.

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