Informatics Publishing Limited

T. Thillaikkarasi ¹, A. Jagadeesan ², K. Duraiswamy ³

Affiliations
1 Department of Computer Science and Engineering, Bannari Amman Institute of Technology, Sathyamangalam-638 401, Tamil Nadu, IN
2 Bannari Amman Institute of Technology Sathyamangalam-638 401, Tamil Nadu, IN
3 K.S.R. College of Technology, Tiruchengode, Tamil Nadu, IN

Abstract

This paper describes the development of a Multiprocessor System-on-Chip (MPSoC) with a novel interconnect architecture incorporating memory allocation. It addresses the problem of mapping a process network with data dependent behavior and soft real time constraints onto the heterogeneous multiprocessor System on Chip (SoC) architectures and focuses on a memory allocation step which is based on an integer linear programming model. An application is modeled as Kahn Process Network (KPN) which makes the parallelism present in the application explicit. The main contribution of our work is an MILP based approach which can be used to map the KPN of streaming applications with data dependent behavior and interleaved computation and communication. Our solution minimizes hardware cost while taking into account the performance constraints. One of the salient features of our work is that it takes into account the additional overheads because of data communication conflicts. It permits to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application.

Keywords

Application Specific Multiprocessors, Integer Linear Programming, Kahn Process Networks, System on Chip.

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A. Jagadeesan ¹, T. Thillaikkarasi ¹, K. Duraiswamy ²

Affiliations
1 Bannari Amman Institute of Technology, Sathyamangalam-638401, Tamil Nadu, IN
2 K.S.R. College of Technology, Tiruchengode-637209, Tamil Nadu, IN

Abstract

Human users have a tough time remembering long cryptographic keys. Hence, researchers, for so long, have been examining ways to utilize biometric features of the user instead of a memorable password or passphrase, in an effort to generate strong and repeatable cryptographic keys. Our objective is to incorporate the volatility of the user's biometric features into the generated key, so as to make the key ungues sable to an attacker lacking significant knowledge of the user's biometrics. We go one step further trying to incorporate multiple biometric modalities into cryptographic key generation so as to provide better security. In this article, we propose an efficient approach based on multimodal biometrics (Iris and fingerprint) for generation of secure cryptographic key. The proposed approach is composed of three modules namely, 1) Feature extraction, 2) Multimodal biometric template generation and 3) Cryptographic key generation. Initially, the features, minutiae points and texture properties are extracted from the fingerprint and iris images respectively. Subsequently, the extracted features are fused together at the feature level to construct the multi-biometric template. Finally, a 256-bit secure cryptographic key is generated from the multi-biometric template. For experimentation, we have employed the fingerprint images obtained from publicly available sources and the iris images from CASIA Iris Database. The experimental results demonstrate the effectiveness of the proposed approach.

Keywords

Biometrics, Multimodal, Fingerprint, Minutiae Points, Iris, Rubber Sheet Model, Fusion, Segmentation, Cryptographic Key, Chinese Academy of Sciences Institute of Automation (CASIA) Iris Database.

Full Text

     

T. Thillaikkarasi ¹, A. Jagadeesan ¹, K. Duraiswamy ²

Affiliations
1 Bannari Amman Institute of Technology, Tamil Nadu, IN
2 K.S.R.College of Technology, Tiruchengode, Tamil Nadu, IN

Abstract

This paper describes the development of a Multiprocessor System-on- Chip (MPSoC) with a novel interconnect architecture incorporating memory allocation. It addresses the problem of mapping a process network with data dependent behavior and soft real time constraints onto the heterogeneous multiprocessor System on Chip (SoC) architectures and focuses on a memory allocation step which is based on an integer linear programming model. An application is modeled as Kahn Process Network (KPN) which makes the parallelism present in the application explicit. The main contribution of our work is an MILP based approach which can be used to map the KPN of streaming applications with data dependent behavior and interleaved computation and communication. Our solution minimizes hardware cost while taking into account the performance constraints. One of the salient features of our work is that it takes into account the additional overheads because of data communication conflicts. It permits to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application.

Keywords

Application Specific Multiprocessors, Integer Linear Programming, Kahn Process Networks, System on Chip, Memory Allocation.

Full Text