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Sarvanan, S.
- Design and Implementation of a Fractional Bit Encoded Spatial Modulator for the Versatile Multiple-Input Multiple Output (MIMO) System
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Authors
Affiliations
1 Department of Information and Communication Technology, School of Computing, SASTRA University, Thanjavur, TN 613402, IN
2 Department of Information Technology, School of Computing, SASTRA University ,Thanjavur, TN 613402, IN
3 Department of Information Technology, School of Computing, SASTRA University, Thanjavur, TN 613402, IN
1 Department of Information and Communication Technology, School of Computing, SASTRA University, Thanjavur, TN 613402, IN
2 Department of Information Technology, School of Computing, SASTRA University ,Thanjavur, TN 613402, IN
3 Department of Information Technology, School of Computing, SASTRA University, Thanjavur, TN 613402, IN
Source
Programmable Device Circuits and Systems, Vol 2, No 8 (2010), Pagination: 78-83Abstract
In this paper, we present design and field programmable gate array (FPGA) implementation of fractional bit encoded (FBE)–spatial modulation (SM) based transmitter for the multiple-input multiple output (MIMO) system. SM is a novel approach to multiple–input–multiple–output (MIMO) systems which entirely avoids inter–channel interference (ICI) and requires no synchronization between the transmit antennas, while achieving a spatial multiplexing gain. This is performed by mapping a block of information bits into a constellation point in the signal and spatial domains. Fractional bit encoding is modulus conversion scheme which convert the incoming bit stream to numbers in an arithmetic base, or modulus, that is not a power of 2 .When applied to SM, FBE relies on encoding each point in the spatial domain, i.e., the antenna index, with, on average, a non–integer number of bits, while keeping unchanged the encoding process in the signal domain. This results in a more versatile system design allowing transmitter to be equipped with an arbitrary number of antennas for a wider range of spectral efficiencies given restrictions on space and power consumption. It is especially useful for compact mobile devices where cost and space constraints pose fundamental limits on the achievable bit rate. The synthesis results of the implementation of transmitter on FPGA are included in the paper.Keywords
Fractional Bit Encoding (FBE), Inter Channel Interference (ICI), Multiple Input multiple Output(MIMO) System, Spatial Modulation (SM).- Efficient Location and Capacity Planning of Node B for 3G Networks
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Authors
Affiliations
1 School of Electronics Engineering, VIT University, Chennai – 600127, Tamil Nadu, IN
2 School of Electronics Engineering, VIT University, Chennai – 600127, Tamil Nadu
3 RF Planning, Bharti Airtel Ltd, Chennai - 600028, Tamil Nadu, IN
4 Middlesex University, London, NW4 4BT, United Kingdom
1 School of Electronics Engineering, VIT University, Chennai – 600127, Tamil Nadu, IN
2 School of Electronics Engineering, VIT University, Chennai – 600127, Tamil Nadu
3 RF Planning, Bharti Airtel Ltd, Chennai - 600028, Tamil Nadu, IN
4 Middlesex University, London, NW4 4BT, United Kingdom