Informatics Publishing Limited

M. Janaki Rani ¹, S. Malarkkan ²

Affiliations
1 Area of Low Power VLSI Design in Sathyabama University, Chennai, IN
2 Manakula Vinayagar Institute of Technology, Puducherry, IN

Abstract

As the VLSI technology and supply/threshold voltage keep on reducing, leakage power has turn out to be highly important in the power wastage of present CMOS circuits. In order to reduce the leakage current is evolving as very significant in low-power design. This provides great opportunity for the researchers to look for better technique to reduce the leakage power. Several methods thus have been provided by the researchers to decrease the leakage power consumption. Input Vector Control (IVC) method is depends on the inspection that the leakage power in a CMOS logic gate is based on the gate input state and a good input vector has a capability to decrease the leakage current when the circuit is in the sleep mode. This technique is found to be better technique for leakage power reduction. When paths in circuits happen to deeper, the input vector control techniques turn out to be unsuccessful since gates with deep levels are difficult to be affected by the input vector. One way to handle this problem is the gate replacement method. Gate replacement technique is nothing but replacing a gate with another gate with sleep mode attached in it. This paper combines IVC and gate replacement technique for better reduction in leakage current. The simulation result shows that the proposed technique resulted in better reduction in leakage current when compared to conventional techniques.

Keywords

Leakage Current, Input Vector Control (IVC), Gate Replacement, Worst Leakage State (WLS).

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B. Sathyabama ¹, S. Malarkkan ²

Affiliations
1 Area of Low Power VLSI Design in Sathyabama University, Chennai, IN
2 Manakula Vinayagar Institute of Technology, Puducherry, IN

Abstract

One of the significant factors for evaluating the circuit performance is transistor sizing. Thus for offering better evaluation, an optimal size of transistor is required. The purpose of the optimization is to reduce the power-delay product or the energy requirement by the circuit. The power and delay are mainly based on the size of transistor. There are many technique exists for optimizing the size of transistor for reducing the power consumption. But all these techniques resulted in poor performance for larger transistors. To overcome those demerits, genetic algorithm is used. Genetic algorithm has the capacity of minimizing the search problem complexity uses the transistor sizing which is usually a type of search problem in the large multidimensional search space for energy reduction. This technique shows better performance when compared to the Hybrid Tree Structure technique. For further improving the performance, a modified genetic algorithm is proposed in this paper for determining the transistor size which in turn leads to better reduction of power consumption.

Keywords

Transistor Sizing, Power Optimization, Modified Genetic Algorithm.

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R. Narmadha ¹, S. Malarkkan ²

Affiliations
1 Sathyabama University, Chennai, IN
2 Manakula Vinayagar Institute of Technology, Madagadipet, Puducherry, IN

Abstract

For future heterogeneous system the security is the one of the most important problem. Interworking of Universal Mobile Telecommunication Systems (UMTS) and wireless local area networks (WLANs) establishes new challenges in the design of secured protocol. Our approach focuses on Public Key Infrastructure (PKI) to be integrated in beyond 3G network. The Extensible Authentication Protocol –Transport layer security (EAP-TLS) protocol is a standard framework supporting multiple types of authentication methods and it provides a certificate based mutual authentication. This paper analyzed the modification of Extensible Authentication Protocol-Authentication key agreement (EAP_AKA) mechanism based on EAP-TLS. In addition the performance of this modified protocol is analyzed with authentication cost under different mobility and traffic pattern.

Keywords

UMTS-WLAN, EAP-TLS, EAP-AKA.

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M. Janaki Rani ¹, S. Malarkkan ²

Affiliations
1 Sathyabama University, Chennai, IN
2 Manakula Vinayagar Institute of Technology, Puducherry, IN

Abstract

Leakage current optimization is one of the most important design criteria in current-day VLSI chips. In this paper different standby leakage reduction techniques like MTCMOS power gating, self-adjustable voltage level circuit, reverse body bias and transistor stack are proposed. The above techniques are applied to various designs of full adder cells using 28T, 24T, 10T, SERF adder, CLRCL adder and 4-bit adder circuits. This work analyses the leakage current of the circuits by varying the supply voltage from 0.5v to 1.0v. The delay in the sum and carry outputs after applying the reduction techniques are analyzed for the full adder cell. The output voltage levels of the adder cells are tabulated. The circuits are simulated using HSPICE in 90 nm process technology using BSIM4 MOSFET models. The effect of temperature on leakage current is also observed by varying the temperature from 25°C to 100°C. The leakage current decreases with all the proposed methods and the reduction are more with MTCMOS power gating technique.

Keywords

Full Adder Cell, Leakage Current, MTCMOS Power Gating, Reverse Body Bias, Transistor Stack.

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U. Anitha ¹, S. Malarkkan ², J. Premalatha ³, P. Grace Kanmani Prince ³

Affiliations
1 Department of Electronics and Control Engineering, School of Electrical and Electronics Engineering,Sathyabama University, Rajiv Gandhi Salai, Jeppiaar Nagar, Chennai - 600 119, Tamil Nadu, IN
2 ManakulaVinayagar Institute of Technology, Kalitheerthalkuppam, Puducherry – 605107, IN
3 Department of Electronics and Control, Faculty of Electronics, Sathyabama University, Rajiv Gandhi Salai, Jeppiaar Nagar, Chennai - 600 119, Tamil Nadu, IN

Abstract

The technique which uses sound waves to navigate, communicate or detect objects under the surface of sea water is commonly known as SONAR. Recognition and interpretation of objects is an important task in the sonar image processing. The resolution of the examined image is not adequate to classify the objects separately and is mainly affected by the multiplicative noise. The main focus of this work is to implement post-processing technique by entropy filter along with morphological processing for object identification. Relative analysis on the observed results with existing techniques of edge detection implies that the proposed work improves the result of target identification. Furthermore, removal of noise in the sonar image is also discussed in this paper.

Keywords

Edge Detection Operators, Entropy Filter, Morphological Processing, Object Recognition, SONAR.

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S. Semmalar ¹, S. Malarkkan ²

Affiliations
1 Department of Electronics and Communication Engineering, Sri Chandrasekharendra Saraswathi Viswa Mahavidyalaya University, IN
2 Manakula Vinayagar Institute of Technology, IN

Abstract

Proposed the inline EDFA-EYCDFA (Erbium Doped Fiber Amplifier - Erbium ytterbium co doped fiber amplifier) with Quad Pumping for multi wavelength services in optical communication systems using WDM technology. The proposed inline EDFA-EYCDFA model simulated by dual forward and backward pumping, dual-backward pumping, Tri-single forward and dual backward pumping and Quad-single forward and tri-backward pumping with respect to Pump power and fiber Length. The parameters Input optical power, output optical power, Gain, Noise figure, Forward noise power and backward noise power measured from all the types of pumping techniques from that the proposed inline EDFA-EYCDFA with Quad pumping gives high strength gain output with less forward noise power and backward noise power. Quad pumping is the best model suitable for multiple wavelength services in optical communication. The Results shown in Quad pumping Gain is maximum 28 dB and Forward Noise power is less -42.9dBm with the pump power of 20dB and fiber Length 5m.

Keywords

Multiple Wavelength Services, EDFA, EYCDFA, WDM, Gain, Amplified Optical Power, Forward Backward Noise Power.

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