Informatics Publishing Limited

A. Priya ¹, N. Rajesh ², R. Muthaiah ¹

Affiliations
1 School of Computing (VLSI), SASTRA University, 613401, Thanjavur, Tamilnadu, IN
2 School of EEE, SASTRA University, 613401, Thanjavur, Tamilnadu, IN

Abstract

This paper presents carrier synchronization in software defined radio for 8PSK technique. Software Defined Radio (SDR) plays a major solution for the need for flexibility, upgradability, and the problems of implementing multiple radio standards alternatively and even running several services in parallel. Previously carrier synchronization in software defined radio is implemented using QPSK technique and synchronization is done using PLL concept. The drawback in this we can transmit only few (only two) number of bits while synchronization is performed. The carrier synchronization by software defined radio using 8PSK technique will allow more number (three) of bits during synchronization, and the same bandwidth which is used for QPSK technique. The main advantage is the transmitting of three bits which reduces the time consumption and the synchronization is performed using COSTAS LOOP. The purpose and advantage of Costas loop compared to PLL is error voltage. The error voltage is less in Costas loop, due to this synchronization is performed effectively. The complete codings are coded using MATLAB.

Keywords

Software Defined Radio, 8PSK, Costas Loop

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A. Sasikumar ¹, R. Muthaiah ¹

Affiliations
1 School of Computing, Information Communication Technology, SASTRA University, Thirumalaisamudram, Thanjavur - 613401, Tamil Nadu, IN

Abstract

Analog circuits are the most important parts in many Integrated Circuit (IC) design. This paper reviews the basic concepts in analog design automation using evolutionary algorithm. Analog design problem is a multi objective problem; this can be solved by Evolutionary computation methods. Computation methods provide the set of feasible solutions for the optimal circuit design of analog integrated circuits. It is necessary to integrate both analog and digital in a single chip for real world communication. Due to system level integration we need analog design automation tool for IC design. This paper summarized recent start of art in analog optimization and also lists the survey of main people working in this field. Finally, we listed several open research problem to improve the analog design automation for analog IC using evolutionary computation.

Keywords

Analog Design Automation, Analog Integrated Circuits, Evolutionary Computation, Multi Objective.

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K. Saranya Devi ¹, R. Muthaiah ¹

Affiliations
1 School of Computing, SASTRA University, Thirumalaisamudram, Thanjavur, IN

Abstract

This paper presents about the partially parallel encoder and decoder architecture for polar-codes using register-free technique. In this paper, the folding transformation technique and register minimization technique are used for this architecture to reduce the circuit and timing complexity. In general, the polar codes are referred to a low complexity code to achieve the performance of channel carrying capacity in a binary-input memory-less channels. In the fully-parallel architecture, the hardware complexity is the major drawback which is high whereas in partially-parallel architecture the memory-sharing concept is utilized to overcome the complexity of hardware to attain the high throughput application. Thus, the temporary end results are saved within the registers instead of memories and multiplexers to manage the interlocking wires. Hence, the register aspect in polar code centered encoder and decoder architecture are eliminated. In an effort to support the information transmission efficiency stage, we get rid of the knowledge storage side (d-register) in stage-three and stage-four encoder and decoder method. Finally we reduce the 32 register elements for every data transmission process and mainly focus on the data storage and transmit function. Because the storage events are need to more time for data passing to one stage level to another stage.

Keywords

Partially-Parallel, Polar Codes, Polar Encoding, Register Free Technique.

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S. Varthini ¹, R. Muthaiah ¹

Affiliations
1 PG Scholar, School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Abstract

A competent architecture for IIR filter is designed. It is configured and folded, which will be used in the real time applications like loud speaker and equalization of digital signal processing. A basic feature of digital signal processing is filtering. Filtering is a choosy system which passes an assured choice of frequency and attenuating the others frequency. Digital filtering is a prevailing sector of DSP allied works. A system of digital filter performs mathematical operations on a sampled or discrete time variant signal to contract or improve certain aspects of that signal. The configurable folded IIR filter for sixth order is designed using three series of second order IIR filter. This IIR filter architecture is used to carry out three second order or a one sixth order. It can be also used to execute one fourth order and one second order in parallel according to the requirement where, each second order IIR filter is designed using multiply accumulate circuit which as floating point. Here pipelining of IIR filter for second order is proposed to increase the throughput by reducing the critical path delay. The proposed sixth order IIR filter using three second order IIR filter with pipelining achieves 39.7% of increased throughput and it operates at high frequency of 85.068MHz compared with conventional MAC based architecture.

Keywords

IIR Filter, Multiply Accumulate Circuit (MAC), Pipeline.

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S. Sopna ¹, R. Muthaiah ²

Affiliations
1 School of Computing, SASTRA University, Thirumalaisamudram, Thanjavur – 613401, Tamil Nadu, IN
2 Information and Communication Technology, School of Computing, SASTRA University, Thirumalaisamudram, Thanjavur – 613401, Tamil Nadu, IN

Abstract

The main objective of the paper is to improve the throughput and increase the speed of the XTEA (Extended Tiny Encryption Algorithm) which is one of the cryptographic algorithms. The technique used to improve the throughput is parallel processing. In previous, they have used pipelining which increases the overhead that is not desirable. The error detection scheme employed in this paper is RERO (Recomputing with Rotated Operand). The previous error detection REPO (Recomputing with Permuted Operands) occupies more memory than RERO. The embedded systems have been developing with many sensitive nodes like Nano-sensors, Radio Frequency Identification tags, etc. As these systems have many constraints, the required security is given by the light weight block ciphers like PRESENT, XTEA and SIMON. These block ciphers are more suitable for these embedded systems when compared to Advanced Encryption Standard (AES). Providing security alone does not give assurance for their reliability while these architectures are liable to malicious and natural faults. Due to hardware failures, various types of faults occur while implementing in hardware. To overcome this, there are many schemes for error detection that can be applied to these ciphers. One of the error detection schemes is RERO (Recomputing with Rotated Operands). Through RERO, error coverage is achieved high. Parallel processing is applied to the XTEA algorithm to increase the throughput. The two halves that are used in the XTEA algorithm are executed at the same time through the parallel processing. Finally, this algorithm is implemented in the Altera FPGA (Field Programmable Gate Array). The throughput is increased by 60% when compared to previous systems that use sub pipelining. This type of structure finds its application in low resource embedded systems having sensitive nodes like RFID tags and Nano sensors

Keywords

Cryptography, Error Detection, FPGA, RERO, Throughput, XTEA.

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N. Nivedha ¹, R. Muthaiah ¹

Affiliations
1 PG Scholar, School of Computing, SASTRA University, Thirumalaisamudram, Thanjavur – 613401, Tamil Nadu, IN

Abstract

This paper describe about a reduction of area and power using Vertical and Horizontal Common Sub-Expression Elimination Algorithm in ischolar_main raised cosine filter. The common sub-expression elimination algorithm is commonly used to reduce the number of adders present the given multiplier architecture is done by reducing MPIS (Multiplications per Input Samples) and APIS (Additions per Input Samples). In the 2bit and 3-bit BCSE algorithms, shift and add method was proposed. Those provide less area than the normal multiplier. Hence algorithm is proposed to further reduce the area utilization, power consumption .Area is utilized by reducing the number of gates in the architecture. This algorithm used for implementing higher adder filters with very few adders and few stages. The proposed algorithm is used to multiply both the signed and unsigned constant multiplication. Here the adjacent co-efficient are grouped by 2bit, 4bit and 8bit grouping as per the horizontal and vertical common sub-expressions. The Shift and add method is used to reduce the number of adders. Similarly multiplexers are used for switching activity to reduce the adders and multiplication stages. These operations are applied to the RRC FIR filter with the different standards. The whole work is done in Quartus II 9.2 web edition, cyclone III

Keywords

2-bit BCSE, CSE, RRC Filter, VHBCSE Algorithm.

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