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Emerita, R.
- Multi Bit Error Corrections of Parallel FFT by ECC Vs SOS
Authors
Source
Digital Signal Processing, Vol 8, No 7 (2016), Pagination: 206-210Abstract
The Error Corrections Code (ECC) for the parallel transforms is principally focused on the over true of the work .this error correction code does not handle the more designing area of actual designing order to detect and correct errors by the help of algorithmic properties namely Algorithm Based Fault Tolerance technique(ABFT) makes to eliminate the soft errors. the communication system and signal processing system can be implemented with fast fourier transforms by using ABFT techniques .which are consider to be the basic building of all signal processing system.
Keywords
ECC, ABFT, FFT, SPS.
- Implementation of Low Power Architecture of Fixed Point DLMS Adaptive Filter using RCA
Authors
1 Department of ECE, JCT College of Engineering & Technology, Pichanur, Coimbatore, Tamil Nadu, IN
2 Professional Group of Institution, IN
Source
Programmable Device Circuits and Systems, Vol 8, No 11 (2016), Pagination: 310-315Abstract
During this paper, we tend to exhibit a productive engineering for the usage of a delayed minimum mean sq. adaptation filter. The smallest amount Mean sq. (LMS) adaptation filter is that the most prevailing and general adaptation filter, visible of its straight pushiness and satisfactory union execution. Succeeding this LMS calculation doesn't support pipelined execution on account of its dreary conduct; it's modified to a structure known as delayed LMS (DLMS) calculation. A deliberate structure for the execution of a DLMS adaptive filter is proposed in this paper. Existing DLMS filter utilizes carry look ahead adder as a part of request to perform the addition function which brought about area and power utilization issues. For accomplishing range power proficient execution, a swell carry adder is actualized over the tedious combinational squares of the current delayed LMS filter plan. From the design of the carry look ahead adder, it is clear that there is a probability for minimizing the area and power utilization in proposed structure. This work utilizes an uncomplicated and thriving door level amendment to basically diminish the realm and power. This filter set up offers less space delay product (ADP) and less Energy Delay Product (EDP) than the most effective of this structures for filters N=8,16, and 32. Consequently it is clear that the aggregate range power utilization can be diminished to a more prominent degree utilizing the proposed strategy.