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Vanjipriya, P.
- Design of GDI Based Full Adder Circuit for Low Power Applications
Authors
1 Kalaignar Karunanidhi Institute of Technology, Coimbatore, IN
Source
Fuzzy Systems, Vol 7, No 2 (2015), Pagination: 50-53Abstract
Full adder circuit is an essential component for designing of various digital systems. It is used for different applications such as Digital signal processor, microcontroller, microprocessor and data processing units. Due to scaling trends and portability of electronic devices there is a high demand and need for low power and high speed digital circuits with small silicon area. So, design and analysis of low power and high performance adders are of great interest and any modification made to the full adder circuit would affect the performance of the entire system. This paper describes the design and analysis of GDI based 1-bit full adder circuit for low power applications. GDI technique is used to reduce power consumption, propagation delay while maintaining low complexity of logic design. Here we have introduced a 11-T GDI based full adder circuit which can be used for low power applications. The proposed circuit is better than the existing technique in terms of average power and speed with minimum area penalty. Simulations are based on BPTM model and have been carried out by Tanner EDA tool on 180nm, 90nm, 65nm and 45nm technology.
Keywords
Delay, Full Adder, GDI (Gate Diffusion Input), Low Power.
- Design and Implementation of Novel ‘n’-bit Inverter and Buffer using Reversible Gates in QCA
Authors
Source
Digital Signal Processing, Vol 8, No 5 (2016), Pagination: 146-149Abstract
Moore’s law states that the number of transistors that could be integrated into a single die would grow exponentially with time. Thus this causes increasing computational complexity of the chip and physical limitations of devices such as power consumption, interconnect will become very difficult. According to recent analysis the minimum limit for transistor size may be reached. Thus, it may not be possible to continue the rule of Moore’s law and doubling the clock rate for every three years. So in order to overcome this physical limit of CMOS-VLSI design an alternative approach is Quantum dot Cellular Automata (QCA).in inverter and buffers a majority gates plays a vital role. In this survey a novel programmable inverter/buffer using XOR-Logic is taken for analysis and a new programmable novel inverter/buffer is designed based upon QCA technology. This modified novel reversible gates used in the design. This will lead to reduce number of QCA cells so that total area and circuit complexity of inverter/buffer can be minimized compare to previous designs. It also achieves reduced power consumption and high speed performances than all other existing and conventional X-OR gates design which uses normal inverter/buffer.