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Siva Kumar, P.
- An Area Optimized FPGA Implementation for Generation of Phase Coded Pulse Compression Sequences
Abstract Views :225 |
PDF Views:2
Authors
Affiliations
1 ECE Department, Vignan's Institute of Information Technology, IN
2 ECE Department, GITAM University, IN
1 ECE Department, Vignan's Institute of Information Technology, IN
2 ECE Department, GITAM University, IN
Source
Digital Signal Processing, Vol 3, No 9 (2011), Pagination: 428-436Abstract
Pulse compression technique is most widely used in radar and communication areas. The radar pulse compression codes must have good merit factor and discrimination factor. But there are several signal design problems which are reported in the literature and these signal design problems can be solved through binary, Ternary, Quinquenary and six phase pulse compression sequences. Hence VLSI architectures to generate such radar pulse compression sequences were developed. But when we are moving from binary to ternary and ternary to six phase pulse compression VLSI systems, the memory requirements are increased there by the area is increased. The good VLSI design needs optimization of the area, speed, power consumption. This paper concentrates on developing area optimized VLSI architecture to generate radar pulse compression sequences without sacrificing the speed of the system. The other interesting thing about this paper is the proposed single chip VLSI architecture can generate all the phase coded pulse compression sequences like Binary, Ternary, Quaternary, Quinquenary, 6-phase and other poly phase sequences. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability.Keywords
FPGA, Merit Factor, PULSE Compression, Side Lobe Energy, Six Phase Pulse Compression.- Energy Control in 4G Networks
Abstract Views :145 |
PDF Views:0
Authors
Affiliations
1 School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN
2 Department of ECE, Rajalakshmi Engineering College, Chennai- 602105, Tamil Nadu, IN
1 School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN
2 Department of ECE, Rajalakshmi Engineering College, Chennai- 602105, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 35 (2016), Pagination:Abstract
Objective: The design of wireless networks mainly focuses on resource allocation and energy efficient schemes to meet the increasing demands. Methods/Analysis: In this paper, we proposed an algorithm for Resource block (RB) allocation and Transmit power control in Long term evolution (LTE) downlink heterogeneous networks. Findings: Energy efficiency is increased by increasing the number of smaller cells. To satisfy the required user throughput energy efficiency is minimized and suitable resource block allocation is maximized. Novelty/Improvement: In the proposed power control algorithm, user is allowed to select minimum powers to reduce power of Evolved NodeB (eNB).Keywords
Energy efficiency (EE), LTE, Macro (MeNB), Resource Block (RB), Small eNodeB (SeNB).- Luminescence Characteristics of 2-Amino-4,6-Diphenylpyrimidine in Different Solvents and at Various pH
Abstract Views :201 |
PDF Views:0
Authors
Affiliations
1 Department of Chemistry, Annamalai University, Annamalainagar, Tamilnadu, IN
2 Chemistry Section, Annamalai University, Annamalainagar, Tamilnadu, IN
1 Department of Chemistry, Annamalai University, Annamalainagar, Tamilnadu, IN
2 Chemistry Section, Annamalai University, Annamalainagar, Tamilnadu, IN