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Sivasankari, N.
- Effective and Efficient Optimization in RC4 Stream
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Authors
Affiliations
1 Sembodai Rukmani Varatharajan Enginnering College, Sembodai, Tamilnadu, IN
1 Sembodai Rukmani Varatharajan Enginnering College, Sembodai, Tamilnadu, IN
Source
International Journal of Scientific Engineering and Technology, Vol 3, No 6 (2014), Pagination: 826-829Abstract
At present technology, power saving technique is one of the important criteria while designing a hardware for RC4 stream cipher. So this paper proposes a BCD to Excess-3-adder to build an efficient hardware with parallel processing system for low power consumption without compromising the speed and security in cryptography. Loop unrolling and Pipeline concepts are used for expeditious hardware implementation. This design is realized on XC3S100E FPGA with VHDL language.Keywords
BCD to Excess-3-Adder, Cryptography, Loop Unrolling, Pipelining, RC4, Stream Cipher.- Implementation of a Hybrid Ring Oscillator Physical Unclonable Function
Abstract Views :244 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, IN
2 Department of Electronics and Communication Engineering, Kalasalingam University, IN
1 Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, IN
2 Department of Electronics and Communication Engineering, Kalasalingam University, IN
Source
ICTACT Journal on Microelectronics, Vol 4, No 2 (2018), Pagination: 602-607Abstract
Developing a hybrid ring oscillator based Physical Unclonable Function (PUF) in FPGA is the main work of this paper. Each structure has its own virtuous characteristics thus the desirable characteristics are selected from each PUF then they are combined together to get the hybrid PUF structure. Mainly PUF structures are used as random number generator which should be same at all the generation times. This property makes the circuit suitable for secure cryptographic structure applications. In this paper hybrid ring oscillator structure is proposed for enhancing uniqueness and reliability. The experiments were conducted on Xilinx FPGA’s with the certain challenging set and produce unique response only for the concerned chip. In the experimental analysis, the proposed design increases the circuit complexity, but the power consumption seems to be same with the traditional designs.Keywords
Hardware Security, Uniqueness, Random Number Generation, Intrinsic PUFs, IP Protection, IC Authentication.References
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