Informatics Publishing Limited

N. Divya ¹, Y. S. Amaresh ¹, M. K. Naik ¹, D. S. Aswathanarayana ¹, N. M. Shakuntala ¹

Affiliations
1 Department of Seed Science and Technology, University of Agricultural Sciences, Raichur-584 102, IN

Abstract

The antagonistic potential of forty four isolates of Trichoderma were evaluated in vitro against the most widely occurring soil borne plant pathogens viz., Macrophomina phaseolina, Rhizoctonia solani, Rhizoctonia bataticola and Sclerotium rolfsii to identify the most potential Trichoderma isolate. Maximum growth inhibition of M. phaseolina (81.11 %), R. solani (82.59 %) and S. rolfsii (76.67 %) was recorded by T. hamatum where as T. virens was most aggressive against R. bataticola (68.15 %) in dual culture technique.

Keywords

Trichoderma, Rhizoctonia bataticola, Macrophomina phaseolina, Rhizoctonia solani, Sclerotium rolfsii, Biological Control.

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N. Divya ¹

Affiliations
1 YMT college of Management, IN

Abstract

Retaining talent and reducing turnover is consistently a top concern for organizations. Organizations believe that retaining talent will be their largest challenge over the next three to five years. It is observed that one out of every three workers is seriously considering leaving their job. There appears to be a need for organizations to refocus attention on retaining their talent, with respect to career advancement opportunities, employees are looking for opportunities to grow with their jobs and move up within the company-either within their department or across departments. The research focuses on understanding the drivers of employee retention and tools for managing and measuring talent.

Keywords

Retaining Talent, Career Advancement, Measuring Talent.

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S. Sukhumar , S. Sofiya , S. Abinaya , M. Bhuvaneswari , N. Divya , N. Suthanthira Vanitha

Abstract

 This research paper is based on the concept of pedestrian safety while travelling in bus. Due to the continuous development of technology, the establishment of intelligent transport system has become the trend for the development of transport. This paper, by means of integrating advantages of multiple technologies, aims at designing and constituting IT’S mainly to increase the level of utilization, safety and comfort. This is mainly proposed for safer journey using ARM processor. This ARM processor is used because of its low power consumption and high speed. This proposed system consists of RFID reader that ensures the passenger to enter the bus. In addition alcoholic sensor is also used which does not allows the passenger to enter into the bus if he/she supposed to be drink. This alcohol detection will help us to ensure the safety to both men and women. Speed controller is placed inside the bus in order to control the speed of the bus and that information also send to the data base in order to ensure the safe journey. Voice talking GPS inside the bus guides the passenger to identify their departing location, information related to safety, security system, seating arrangement and prevention methods during accident. ZIGBEE plays a role of data transferring and to communicate with the bus. The result of our research idea is done in Auto Cad and the simulations are shown in this paper.

Keywords

ARM Processer, Alcohol sensor, Speed controller, GSM, GPS and ZIGBEE

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K. Thamaraiselvan ¹, C. Gayathri ¹, N. Divya ¹

Affiliations
1 AMS Engineering College, Namakkal, IN

Abstract

A high-speed wide-range parallel counter that achieves high operating frequencies through a novel pipeline partitioning methodology (a counting path and state look-ahead path) is proposed, and can be implemented using only three simple repeated CMOS-logic module types: an initial module generates anticipated counting states for higher significant bit modules through the state look-ahead path, simple D-type flip-flops, and 2-bit counters. The state lookahead path prepares the counting path's next counter state prior to the clock edge such that the clock edge triggers all modules simultaneously, thus concurrently updating the count state with a uniform delay at all counting path modules/stages with respect to the clock edge. The structure is scalable to arbitrary N-bit counter widths (2-to-2N range) using only the three module types and no fan-in or fan-out increase. The counter’s delay is comprised of the initial module access time (a simple 2-bit counting stage), one three-input AND-gate delay, and a D-type flip-flop setup-hold time. Thus the proposed counter can be implemented without AND gate and hence speed can be increased. The design can be implemented with Modelsim simulator. The parallel counter can give a maximum operating speed of 2GHz for 8-bit counter. Finally, the area of a sample 8-bit counter is 78 125 μm² (510 transistors) and power consumption is 13.89Mw at 2GHz.

Keywords

High Performance Counter Design, Parallel Counter Design, Pipeline Counter Design.

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