Informatics Publishing Limited

M. Naveenkumar ¹, Sunil S. Mathad ¹

Affiliations
1 S. D. M. College of Engineering and Technology, Dharwad, Karnataka, IN

Abstract

This paper deals with the design and implementation of a Field Programmable Gate Array (FPGA) based co-processor called Redundant Radix-4 Arithmetic co-processor. In the proposed work different arithmetic operations addition, subtraction, complementation, multiplication, square, division left shift and right shift are implemented. These arithmetic operations are implemented using Redundant Radix-4 (RR-4) number system for achieving high speed. The binary numbers are converted to RR-4 and these numbers are used for arithmetic operations. This RR-4 number system will carry out the operations in parallel. Parallel addition of two m-digit redundant binary numbers can be performed in a same interval of time independent of m, without using propagated carry. The proposed co-processor is developed by set of Very High Speed Integrated Circuit Hardware Description Language (VHDL) modules for fast parallel arithmetic operations. The implementation is done through different stages of Xilinx Integrated Software Environment (ISE) 12.4 and physical verification is carried out on Virtex 5 XC5VLX110T Field Programmable Gate Array (FPGA). The simulation results of co-processor are observed using Xilinx ISim simulator. The co-processor is interfaced with the Chipscope Pro Virtual Input-Output (VIO) console, to enter data from the keyboard and to get back the result in VIO console window. This co-processor occupies area of 2281.52 μm2 and 407.848 MB of memory with switching power 1.02489371 mW.

Keywords

Carry-Propagation Free Adder, Co-Processor, FPGA, VHDL, RR-4, Xilinx ISE.

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M. Naveenkumar ¹, N. P. Suchithra ¹, Jayashree C. Nidagundi ¹, Sunil S. Mathad ¹

Affiliations
1 S. D. M. College of Engineering and Technology, Dharwad, Karnataka, IN

Abstract

In Digital Wireless Communication application, the design of Low Power and High Speed Analog to Digital Converter (ADC) is the need-of-the-day. This paper explores the design of low power and high speed comparator used in all available ADC architectures. This paper aims to design a CMOS comparator with a considerably high speed maintaining its low power consumption with clock as triggering input. The design has been simulated using 0.18 μm CMOS technology to provide better performance verification leading to low power dissipation, high speed and low propagation delay. Simulation results for its functionality have been verified using Cadence Virtuoso tool 6.1.3 version for better comparator results. This paper has been compared with the results of present earlier reported work, and obtained improvement in the present work. The designed comparator consumes 7.849 x 10-12 W of power dissipation from 1.8 v power supply and propagation delay is of 0.058 ns. The comparator layout occupies area is 4 x 11 μm2.

Keywords

ADC, Clock Trigger, CMOS, High Speed, Low Power.

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Koppala Guravaiah ¹, B. Ramakantha Reddy ¹, S. Shiva Prakash ¹, M. Naveenkumar ¹

Affiliations
1 CSE Department, Sree Vidyanikethan Engineering College, Tirupati, AP, IN

Abstract

Team work plays major role in any organization for solving problem. We have many online collaborative systems for team communication. These systems generates huge amount of data. Our main aim is to find the best group and best person among the group. And also specify groups and their facilitators operation and provide feedback also for their outcomes and also specify about the problems. This is done by clustering the communication data and applies the sequential pattern mining technique on that data. By applying this techniques we easily finding that which team work is good and which team member work very well. Also specifies feedback system to week teams through analysing good team pattern mining.

Keywords

Data Mining, Clustering, Sequential Pattern Mining, Team Work, Tracking System (TRAC).

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