Informatics Publishing Limited

V. Venkata Rao ¹, G. Sasibhushana Rao ², M. Madhavi Latha ³, Y. Ravi Kumar ⁴, K. V. N. M. Prasad ⁵

Affiliations
1 Tirumala Engineering College, Narasarao Pet, Guntur (Dist.), Andhra Pradesh, IN
2 Electronics and Communication Engineering Department, Andhra University, Visakhapatnam, IN
3 Electronics and Communication Engineering Department, JNT University, Hyderabad, IN
4 DLRL, Hyderabad, IN
5 Hyderabad, IN

Abstract

The Global Positioning System (GPS) is a worldwide satellite-based navigation system. The usefulness of the system for civilian users was even more pronounced, with the elimination of Selective Availability (SA) on May 2nd, 2000. The GPS accuracy relies in the precise knowledge of the satellite orbits and the time. Each GPS satellite carries an atomic clock to provide timing information for the signals transmitted by the satellites. The clocks are oscillating at a particular frequency. The oscillator clock time and the true time differ from each other both in scale and in origin. The true time reflects the atomic clock time inU.S., which also differs by 15 seconds from Coordinated Universal Time (UTC) by 2010. However, the GPS true time is calibrated byU.S.atomic time. The true time reflects the fact that the times indicated on satellite and receiver clocks are not perfectly uniform and must be calibrated by master atomic clocks on the earth. The typical error in GPS positioning due to the non synchronisation of satellite to UTC is 100 nsec and the corresponding pseudorange error is 30 meters.  The GPS satellites revolve around the earth with a velocity of 3.874 km/s at an altitude of 20,184 km. Thus on account of its velocity, a satellite clock appears to run slow by 7 microseconds per day when compared to a clock on the earth’s surface. But on account of the difference in gravitational potential, the satellite clock appears to run fast by 45µs per day. The net effect is that the clock appears to run fast by 38 µs per day. This is an enormous rate difference for an atomic clock with a precision of a few nanoseconds. In this paper,  the satellite clock error and the relativistic error effect on the navigation solution are carried out by collecting the several days of dual frequency (1575.42.MHz and 1227.6 MHz) GPS receiver data from the Andhra University Engineering College, Visakhapatnam (Latitude/Longitude 17.73oN/83.32oE). From the results an absolute maximum of 50.825µs satellite clock error is observed which corresponds to a pseudorange of 15.247 Km and an absolute maximum of 14.427ns relativistic error is observed which corresponds to a pseudorange of 4.328m.

Keywords

GPS, Satellite Clock Error, Relativistic Effect.

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Raja ¹, M. Madhavi Latha ², E. G. Rajan ³

Affiliations
1 Mahatma Gandhi Institute of Technology, Hyderabad, IN
2 Department of ECE, JNT University, Hyderabad, IN
3 Department of Electrical Engineering of the Indian Institute of Technology, Kanpur, IN

Abstract

Electronic Intelligence (ELINT) provides not only direction of arrival of intercepted signals but also provides immediate warning of threat radars, including surveillance, fire control, targeting and missile guidance systems. Radar signals from across the borders are intercepted by an ELINT receiver, recorded on a magnetic tape and are analyzed by an associated signal processing system to give a wide range of parameters, including direction, type of radar, frequency, frequency agility, Pulse Repetition Frequency (PRF), and PRF type, Scan type, Scan time and Intra pulse modulation details. These parameters are sufficient to characterize the type of emitter, and complete identification is then carried out by comparing the analyzed signal with parameters of hostile and friendly emitter characteristics stored in a library within the computer memory. Analysis of the signals and warning of a threat is virtually instantaneous and enables countermeasures of jamming and/or decoys to be initiated.

Keywords

Electronic Support Measures, ECM, Radar Signal Parameter Estimation.

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Latha Sahukar ¹, M. Madhavi Latha ²

Affiliations
1 Department of Electronics and Communication Engineering, Aurora’s Technological and Research Institute, IN
2 Department of Electronics and Communication Engineering, JNTUH College of Engineering, Hyderabad, IN

Abstract

The modern software defined radios (SDRs) use complex signal processing algorithms to realize efficient wireless communication schemes. Several such algorithms require a specific symbol to sample ratio to be maintained. In this context the fractional rate converter (FRC) becomes a crucial block in the receiver part of SDR. The paper presents an area optimized dynamic FRC block, for low power SDR applications. The limitations of conventional cascaded interpolator and decimator architecture for FRC are also presented. Extending the SINC function interpolation based architecture; towards high area optimization and providing run time configuration with time register are presented. The area and speed analysis are carried with Xilinx FPGA synthesis tools. Only 15% area occupancy with maximum clock speed of 133 MHz are reported on Spartan-6 Lx45 Field Programmable Gate Array (FPGA).

Keywords

Decimation, Interpolation, Sample Rate Conversion, Fractional Rate Conversion.

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Harikishore Kakarla ¹, M. Madhavi Latha ², Habibulla Khan ¹

Affiliations
1 Dept. of ECE, KL University, Vijayawada, AP, IN
2 Dept. of ECE, JNTUH, Hyderabad, AP, IN

Abstract

As with the increase in data density the probability of error happening in data transfer has increased the need for error free coding technique is in greater demand. In this paper an optimal approach for the processing of self correcting logic in faulty condition during coding and decoding operation is developed. The process of digital designing and its evaluation for realization is presented. The implementation of proposed design on Xilinx-FPGA device is presented.

Keywords

Error Free Coding, Memory Operation, Self Correcting Logic, Forward Error Correction.

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