Informatics Publishing Limited

Kiritkumar Bhatt ¹, Saurabh M. Patel ¹, A. I. Trivedi ²

Affiliations
1 ECE Department, Sardar Vallahbai Patel Institute of Technology, IN
2 Electrical Engineering Department, M.S. University, IN

Abstract

Power has become an important aspect in the design of general purpose processors. Hence, to explore how design tradeoffs affect the power and performance of the processor. Proper implementation of pipelining structure at the architectural level may consume less power and help to improve the energy efficiency of the processor, and may dissipate less power for the same performance or higher performance for the same power. Some architectural changes, such as pipelining and caching, can significantly improve efficiency. Unfortunately many other architectural tradeoffs leave efficiency unchanged. This is because a large fraction of the energy is dissipated in essential functions and is unaffected by the internal organization of the processor. This paper discusses the design and implementation of power optimized parallel pipelined structures of 16-bit CPU on Xilinx Spartan-3E FPGA. A modified processor architecture is proposed to reduce the unnecessary switching activities to achieve significant power reduction.

Keywords

Processor Design, Embedded Processor, Low-Power Architecture, FPGA Implementation.

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Kiritkumar Bhatt ¹, A. I. Trivedi ²

Affiliations
1 ECE Department, SVIT – Vasad, Gujarat, IN
2 Electrical Engineering Department, M S University of Baroda, IN

Abstract

The FPGAs can be configured by the end-user to implement any digital system virtually, which may use millions of gates to be operated at few hundred MHz speed. Because of its reprogrammability, the FPGAs become very popular for the applications where prototyping and economic viability are of great concern. The state-of-the-art fabrication and manufacturing technologies are used to produce the current FPGAs, which comprise of high degree of integration and huge number of transistor count to make it suitable for today’s applications with high performance, but face a power consumption problem. Lower power consumption is a critical design issue in most embedded systems with CMOS technology, where logic switching is a significant factor affecting the system power consumption. The higher the switching frequency the larger the power consumed. This paper discusses the major power consumption sources in VLSI circuit with the primary focus on switching activity, its computation and its power estimation carried out by probabilistic approach.

Keywords

Power Estimation, Probabilistic Approach, Switching Activity, Low Power.

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Kiritkumar Bhatt ¹, A. I. Trivedi ¹

Affiliations
1 Department of Electrical Engineering, M S University of Baroda, Gujarat, IN

Abstract

To avail a longer battery life is a major constraint in the area of digital circuit design where complexity increases as per the Moore’s law. With the evolution of CMOS technology, it was believed that power consumption problem has been solved because static power consumption is very low and designers where focusing mainly on performance and area. But with the reasonable increase of device density per unit area the power consumption becomes considerably high. This is absolutely true for FPGAs, where power consumption noticeably rises due to the increase in the clock frequency, chip area and the ability to be programmed. FPGAs formed by three different technologies such as pure CMOS, Pass transistors and SRAM based. It becomes very popular because it takes very less development time, instant prototyping and less back end process. Hence, power consumption estimation and then optimisation has become very important. Looking to these facts this paper will explain the total power consumption model for CMOS based FPGAs because the power estimation is basic requirement for power optimized implementation on FPGAs.

Keywords

CMOS, FPGA, Optimization, Power Model.

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Dilip H. Patel ¹, Kiritkumar Bhatt ², Jaymin Bhalani ³

Affiliations
1 Department of Electronics and Communication Engineering, LDRP Institute of Technology and Research, IN
2 Department of Electronics and Communication Engineering, Sardar Vallabhbhai Patel Institute of Technology, IN
3 Department of Electronics and Communication Engineering, Babariya Institute of Technology, IN

Abstract

In Optical Burst Switched (OBS) Networks, data is transported in a bufferless network and hence there is fair amount of possibility of contention among the data bursts. This occurs when multiple bursts contend for the same link. The existing reactive contention resolution schemes attempt to address issue of contention without making any efforts to minimize the occurrences of contention in the network. Also, the existing proactive contention minimization schemes fail to provide improvement in contention loss at a very high load. Therefore, we are presenting new scheme for reducing the occurrence of contention in OBS network and it is known as Dynamic Hybrid Cluster and Deflection Feedback (DHCF) scheme. In proposed DHCF scheme entire OBS network is partitioned into many small clusters. In each cluster, one node acts as cluster head for gathering the information of resources in the network. The contention is minimized using clustering approach and it can be further improved with the help of deflection feedback mechanism. A performance metrics is considered to evaluate merits of the proposed DHCF scheme and its effects on overall network performance. Also, the comparison of the performance of the DHCF scheme with limited hybrid deflection and retransmission (LHDR) scheme and dynamic hybrid retransmission in deflection routing (DHRD) scheme is made. The simulation results show that the proposed scheme gives improvement in Burst Loss Probability (BLP) in the range of 31% to 38% and delay improvement in the range of 64% to 74% on vBSN network. The vBSN is network topology.

Keywords

Optical Burst Switching, Contention Resolution, Burst Loss Probability (BLP).

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