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Deshmukh, Khemraj
- A 90nm Low Noise Amplifier Using Active Inductor for Ultra Wideband Application
Authors
Source
Programmable Device Circuits and Systems, Vol 8, No 6 (2016), Pagination: 161-164Abstract
This paper presents a LNA for UWB radio receiver at 2 to 6GHz victimization 0.09µm TSMC Technology wherever 009µm technology is for lower power consumption. UWB radio that created up in between the frequency vary of 2GHz to 6GHz.The basic design of LNA includes a RF electronic equipment within the middle of input matching network and also the output matching network. We’ve designed a LNA that consist low noise figure, good input and output resistivity matching and high gain and stability LNA, wherever operative temperature is 27 ºC gain is 20dB and would have smart stability. we have a tendency to used ltspice tool for the simplest performance and accuracy for results, this work represents associate LNA schematic compose of Common source LNA and Cascode LNA, wherever Common source LNA is employed for glorious input and output matching and also the cascode LNA for low Noise figure and high gain, an extra feature is that single terminated LNA employs inductive supply degeneration conception (inductor Ls is connected to the supply of semiconductor device M1) wherever M1 contains a larger management over the worth of the important a part of the input impedance through the selection of the inductance. Cascode semiconductor device power supply is employed to scale back the interaction of the tuned output with the tuned input.
Keywords
Low-Noise Electronic Equipment (LNA), Frequency (RF) and CMOS, Single Stage Electronic Equipment, Active Passive Component, RF Front.
- Removal of Noises in ECG Signal by using Digital FIR-IIR Filter in VHDL
Authors
Source
Digital Signal Processing, Vol 8, No 5 (2016), Pagination: 135-139Abstract
The structure of the ECG signal is time varying which is the supreme common source used for the purpose of diagnosis & observation and analysis of various types of diseases related to the heart in the patient. ECG recording is the process done by placing the electrodes in the specified positions at body of humans. During the process of recording, a noise distracted signal is applied to ECG signal and the ECG signal is also full of artifacts which always degrades the quality of it and establishes threats in the recording the absolute ECG signal. The artifacts mostly noticed are Power line Interference, Baseline Wander and muscle tremors. Therefore, for accuracy in the characteristics points of ECG, an ECG having good quality is essential. Generally, we notice that these kinds of noises are very common in the process and detection is needed. We found that FIR-IIR filter is giving suitability to increase the quality of it. So, here we are presenting an implementation of the FIR-IIR filter for reduction of artifacts using Xilinx EDA tool and the Power analysis is being done in X-Power analyzer by creating VHDL code and running it into Model Sim 3.1.
Keywords
ECG Signal, FIR Filter, IIR Filter, VHDL, Xilinx, Model Sim 3.1.- Sub-mW Low Noise Amplifier Using Active Inductor for Ultra Wideband Application
Authors
1 Department of ETC, SSTC, SSGI, Bhilai, IN
2 Department of E&I, SSTC, SSGI, Bhilai, IN
Source
Artificial Intelligent Systems and Machine Learning, Vol 8, No 8 (2016), Pagination: 275-278Abstract
In this paper we work on the control of total power consumption of a low noise amplifier using unique design of CMOS active inductor (on chip) for the low voltage RF circuit. We tried to address a replacement methodology of passive inductors by Active Inductors (AI) to improve the circuit performance. And improved parameter like power potency, Noise Figure (NF) and alternate methodology of input and output matching of 50 ohm. Exploiting the new biasing metric, and new design methodology of 1.8v supply, leads to 5.4mW total DC power consumption. We uses 180nm CMOS technology, frequency range of 2-6GHz. This simulation offers the thought of the longer term analysis to design higher LNA in terms of low power consumption, stability and higher range of frequency of operation.
Keywords
CMOS, IC (Integrated Circuit), LNA (Low Noise Amplifier) Low Power, Low Voltage, Stability, RF (Radio Frequency), S-Parameter, ULP (Ultra Low Power).- A Power Efficient Pulse Triggered Flip-Flop by X-OR Based Clock Gating Scheme at 32nm Technology
Authors
1 Department of ETC, SSTC, SSGI (FET), Bhilai, IN
Source
Programmable Device Circuits and Systems, Vol 9, No 4 (2017), Pagination: 70-73Abstract
A continuous increase in number of transistors and operating frequency causes high power dissipation. The most important task to minimize the power is optimization of power at the logic level. This paper presents a novel power efficient pulse triggered flip-flop. Proposed flip-flop use Exclusive-or gate based clock gating scheme that reduce the power dissipation by disabling the clock signal in inactive portion of chip. In this paper replica path delay pulse generator is used to simplify the design effort. This paper presents a comparison of existing flip-flop in term of power dissipation for different input patterns. The operation of flip-flop is analyzed and is simulated using Tanner EDA in 32nm technology at room temperature in schematic level. Simulation result shows the sensible power dissipation reduction.
Keywords
Pulse Triggered Flip-Flop, Low Power, Clock Gating, Sequential Circuit, Dynamic Power, 32 nm Bulk CMOS, Pulse Generator, CMOS Logic.- Design of a Low-Power & Lower-Delay 8-Bit SRAM Cell Using Pulsed Latch Circuit in 32nm Technology
Authors
1 Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, IN
Source
Programmable Device Circuits and Systems, Vol 9, No 5 (2017), Pagination: 110-115Abstract
This paper describes a low-power and lower-delay SRAM (Static Random-Access Memory) Cell using pulsed latch circuit. The delay and power consumption of conventional SRAM Cell is reduced by replacing two NMOS access transistors with pulsed latch circuit. The main aim of the pulsed latch circuit is to reduce delay and increase the speed of the design. As, SRAM Cell is one of the basic building element of VLSI design and due to its huge demand in VLSI chips, it is necessary to reduce power and delay so as to increases the speed of the SRAM Cell. In this paper 1bit, 4bit and 8bit SRAM Cell are designed with pulsed latch circuit and their performance is compared with conventional SRAM Cell design. The conventional SRAM and proposed SRAM Cell, both designs are implemented in 32nm CMOS technology with Vdd = 1.0V in Tanner tool v16.0. In comparision with conventional SRAM Cell the proposed SRAM Cell is much better in terms of power, speed and performance. In the proposed SRAM Cell design delay reduces drastically as compared to that of the conventional SRAM Cell.
Keywords
SRAM Cell, Pulsed Latch Circuit, Speed, Low-Power, Lower-Delay, CMOS Technology, NMOS Access Transistors, 32nm Technology, Tanner Tool.References
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- A Review on Low Power Design Techniques of Flip-Flop
Authors
1 Department of Electronic and Telecommunication Engineering, SSTC, SSGI (FET), Bhilai, IN
Source
Programmable Device Circuits and Systems, Vol 9, No 6 (2017), Pagination: 129-132Abstract
In past low power design techniques were not primary constraint because device density and operating frequency were low. Nowadays because of very large scale integration, millions of transistors are fabricated on a single chip and requirement of high performance, portable, battery based devices causes need of low power design techniques. Digital circuits are two types: combinational circuit and sequential circuit. Sequential circuit mainly consists of flip-flops. Flip-flop is basic storage element and consume large amount of power because they are clocked with system operating frequency. Clock system consists of clock distribution network and flip-flops are most power consuming subsystems. Because of continuous increase in chip complexity and operating frequency reduction of power is long-winded task. After studying various journals and conferences, in this paper various low power Flip-flop design techniques are presented.
Keywords
Pulse Triggered Flip-Flop, Low Power, Clock Gating, Sequential Circuit, Dynamic Power, Leakage Power, Dual Supply, CMOS Logic.References
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