Informatics Publishing Limited

S. Suryanarayana ¹, B.L. Deekshatulu ², K. Lal Kishore ³, Y. Rakesh Kumar ⁴

Affiliations
1 Dept of ECE, ACE Engg.College, Hyderabad, A.P, IN
2 Hyderabad Central University, Hyderabad, A.P, IN
3 R&D, JNTU, Hyderabad, A.P, IN
4 Dept of ECE, GNITS, Hyderabad, A.P, IN

Abstract

In this paper a novel algorithm for Gaussian noise estimation and removal is proposed by using 3x3 sub windows in which the test pixel appears. The standard deviation(STD) for all sub-windows are used to define reference STD(σ_ref)and minimum(σ_min) and maximum (σ_max) standard deviations. The average STD (σ_avg) is then calculated as the average of those STDs of all sub-windows whose STD falls with in the range of [σ_min, σ_max]. This σ_avg is used for detecting and removing additive Gaussian noise. The performance is compared with that of the standard mean filter. The proposed scheme is outperforming than the standard mean filter.

Keywords

Additive Gaussian Noise, Standard Deviation, Sub-windows

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Hemalatha Rallapalli ¹, K. Lal Kishore ², G. Harikrishna ³

Affiliations
1 Osmania University, College of Engg., Hyderabad, IN
2 Dept. of ECE, Jawaharlal Nehru Technological University JNTU, Hyderabad, IN
3 Osmania University, Hyderabad, IN

Abstract

This paper documents the design of a SDR Platform asa research tool. In order to keep costs to a minimum and provide the maximum flexibility a processor-less architecture is chosen. All signal processing is carried out using a standard notebook computer.The platform consists of hardware element base band transmitter (OFDM). Software defined radio perform itsprocessing through software (error correction, modulation, control over RF hardware…).The actual and next communication schemes tend to use OFDM systems in order to provide high baud rates and less inter-symbol interference. Fast converging methods to estimate the significant multipath components in fading wireless channels.

Keywords

OFDM, SDR, Time Division Multiple Access, CDMA, Digital Video Broadcasting, Digital Audio Broadcasting.

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C. Ashok Kumar ¹, B. K. Madhavi ², K. Lal Kishore ³

Affiliations
1 ECE dept, TRR Engg. College, Hyderabad, AP, IN
2 ECE Dept., SNIST, Ghatkesar, Hyderabad, AP, IN
3 JNTU College of Engg., Kukatpally, Hyderabad, IN

Abstract

These papers focus on the development of low power VLSI design methodology on system level modeling and circuit level modeling for power optimization. The developed transition optimization approach further merged with circuit level power optimization using Glitch minimization technique. A resistive feed back method is developed for the elimination of glitches in the CMOS circuitry, which result in power consumption and reducing performance of VLSI design. The optimized sequence is then processed through a 8-bit register bank modeled in CMOS level for data transfer to observe the glitch effect. Tanner EDA tool is used for the designing of the CMOS circuitry with resistive feedback mechanism for power optimization.

Keywords

Low Power VLSI, Glitch Free Modeling, Resistive Feedback Logic, Stray Capacitance.

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M. Lakshminarasimhacharyulu ¹, Murthy Sarma ², K. Lal Kishore ³

Affiliations
1 GPCET, Kurnool, IN
2 BVCE, Odalarevu, IN
3 JNTUA, IN

Abstract

EM1 noise reduction is generally accomplished by three means: suppression of noise source, isolation of noise coupling path, and filter shielding. In this paper, another means of EMI noise reduction is proposed is Simultaneous switching noise (SSN) has become an important issue for generation of EMI effect in the design of the internal on chip power distribution networks in current very large scale integration/ultra large scale integration circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.

Keywords

Integrated Circuit Interconnection, On-Chip Inductance, Power Distribution Network, Simultaneous Switching Noise.

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M. L. N. Acharyulu ¹, N. S. Murthysarma ², K. Lal Kishore ³

Affiliations
1 JNTUH, IN
2 SNIST, Hyderabad, IN
3 JNTUA, IN

Abstract

One of the new technique which is notable for dealing problems such as high frequency effect due to inductance and capacitance in physical layout level other than existing of techniques. For most designs for the use of 45nm processing technology the analysis using a static approach is no longer sufficient and it becomes mandatory to analyse the actual variation of the supply voltage with respect to time for detecting chip failure conditions. In this paper we deal with the IR drop analysis of the Diagonal power grid and orthogonal power grid, comparison between the diagonal and orthogonal power grid. Full chip Diagonal power grid static and dynamic IR drop analysis optimization of power in vlsi digital design using red hawk for nanometer era.

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