Informatics Publishing Limited

Irfan Ahmed Usmani ¹, Arshad Aziz ², Muzaffar Rao ³, Razia Zia ³

Affiliations
1 Department of Electronic Engineering, University of Tabuk, SA
2 Department of Electrical & Electronic Engineering, NUST, Karachi, PK
3 Department of Electronic & Computer Engineering, University of Limerick, IE

Abstract

FIR Filter is a fundamental function in many applications, mainly in the field of Digital Signal Processing (DSP). The main problem of this function is its computational complexity, needed to process a signal. Currently, FPGAs are widely used for a variety of computationally complex applications. New generation of FPGAs contain not only basic configurable logic resources but also complex embedded resources. The FPGA implementation of FIR filters based on customary design & techniques utilizes extensive hardware resources, which does not comply circuit scale and system speed. In this paper we investigated the resource utilization and system speed of a new implementation of FIR Filter using DA architecture with and without use of embedded component like DSP units. The filter is designed and Co-simulated with the help of ‘filte r design HDL Coder’ and then synthesized using Xilin x ISE 13.3 Design suit. Result shows that DA based FIR filter design that utilizes basic logic resources gives better performance and efficient resource utilizat ion in comparison with the design utilizing DSP components.

Keywords

FPGA, Discrete Arithmetic, FIR, HDL Coder.

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