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Tamilselvi, G.
- Analysis of Current Mode Logic High Speed CMOS Technology
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Authors
Affiliations
1 Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, IN
1 Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, IN
Source
Biometrics and Bioinformatics, Vol 10, No 2 (2018), Pagination: 34-36Abstract
We have designed D-latch circuit which is suitable for nanometer technology. The circuit is low-voltage and also high speed. Here we are using Current Mode Logic (CML) technique. This technology is used for improve the speed of the D-latch circuit. We are comparing a two-stage frequency divider designed using both the triple-tail DFF and the proposed folded DFF. During the simulation minimum delay was obtained with the help of proposed folded DFF and it consumes the less amount of power. The delay is reduced and the speed is improved. In the DFF, the maximum operating frequency is achieved over a triple- tail DFF. The simulation is done using cadence virtuoso tool.
Keywords
Current Mode Logic (CML), D–Latch, D–FlipFlop (DFF), Nanometer CMOS.
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