Informatics Publishing Limited

E. Chitra ¹, T. Vigneswaran ¹

Affiliations
1 Electronics and Communication Department, SRM University, Chennai, IN

Abstract

This research work presents an efficient implementation of Finite Impulse Response Filter (FIR) using Distributed Arithmetic (DA) architecture. Here, the multipliers in FIR filter are replaced with multiplier less DA based technique. The DA based technique consists of Look Up Table (LUT), shift registers and scaling accumulator. Analysis on the performance of various orders of the digital FIR filter with various methods of sections on different address length of partial tables are done using Xilinx 12.3 synthesis tool. The proposed architecture provides an efficient Very Large Scale Integration (VLSI) implementation which involves significantly less latency and less area-delay complexity when compared with existing structures of the digital FIR Filter. In this method, the multiplier less FIR filter is implemented using Distributed Arithmetic which consists of Look Up Table and then its partitioning is involved. This technique reduces the delay by 15%, area by 34% and LUT by 75%.

Keywords

Distributed Arithmetic (DA), Finite Impulse Response (FIR), Field Programmable Gate Array (FPGA), Look up Table (LUT).

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E. Chitra ¹, T. Vigneswaran ²

Affiliations
1 Department of Electronics and Communication Engineering, SRM University, Kanttankulathur - 603203, Tamil Nadu, IN
2 School of Electronics Engineering, VIT University, Chennai Campus, Chennai - 600127, Tamil Nadu, IN

Abstract

Background/Objectives: FIR filters play a vital role in signal processing applications. This research work presents a low power and high speed efficient buffer based Distributed Algorithms and it is analyzed with Electro Cardio Gram (ECG) signal Finite Impulse Response (FIR) filter design. Methods/Statistical Analysis: The proposed FIR filter is designed using buffer based DA and it is simulated and synthesized using Cadence digital labs. This is compared with different architectures such as conventional DA, separated look up table DA and LUT less DA. Findings: Synthesis report shows that the proposed design has 52% less power dissipation compared with the conventional DA, 21% reduction in delay with separated Look Up Table (LUT) DA and 8% reduction in area with LUT less DA. Conclusion/Improvements: Presently this method is applied for ECG signal input with 16-tap FIR filter. This can be extended for higher order filters to achieve better performance.

Keywords

Distributed Arithmetic (DA), Electro Cardio Gram (ECG), Finite Impulse Response (FIR), Look Up Table (LUT)

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