Informatics Publishing Limited

Durgam Sumalatha ¹, B. Gouri Sivanandini ², T. Sireesha ², R. Maruthi Sivakanth ³

Affiliations
1 Aurora's Engineering College, Bhongir, Nalgonda, AP, IN
2 ECE Dept., Aurora's Engineering College, Bhongir, Nalgonda, AP, IN
3 RGMCET, Nandyal, AP, IN

Abstract

Now a day's VLSI has become the backbone of all types of designs, and in deep sub-micrometer designs the interconnect delay playing vital role in limiting the circuit performance. The same is also limited by crosstalk in an on-chip bus and is highly dependent on the data patterns transmitted on the bus. Till now different crosstalk avoidance coding schemes have been proposed to boost the bus speed and/or reduce the overall energy consumption. Though there are many coding techniques, none of them has been successful in giving a perfect mechanism in mapping of datawords to codewords for CODEC design. It was found that this is mainly due to the nonlinear nature of the crosstalk avoidance codes (CAC). Due to the lack of practical CODEC construction schemes, it has overburdened the use of such codes in practical designs. This work presents guidelines for the CODEC design of the "forbidden pattern free crosstalk avoidance code" (FPF-CAC). The properties of the FPF-CAC have been analyzed and it is showed that mathematically, a mapping scheme exists based on the representation of numbers in the Fibonacci numeral system. The First proposed CODEC design offers a near-optimal area overhead performance. An improved version of the CODEC is then presented, which achieves theoretical optimal performance. The work has been done in investigating the implementation details of the CODECs, including design complexity and the speed. Optimization schemes are provided to reduce the size of the CODEC and improve its speed.  With the proposed technique the delay has been reduced with reference to coded and uncoded bus for different widths.

Keywords

CODEC, Crosstalk, Fibonacci Number System, On-Chip Bus.

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