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Authors
Affiliations
1 Gyancity Research Lab, South City-1 Enclave, Gurgaon - 122001, Haryan, IN
2 GSSI, Italy
3 Aalborg University, Denmark
4 University of Oulu, Finland
5 Gyancity Research Lab, South City-1 Enclave, Gurgaon - 122001, Haryana, IN
Source
Indian Journal of Science and Technology, Vol 9, No 10 (2016), Pagination:
Abstract
Multiplier is used for multiplication of a signal and a constant in Digital Signal Processing (DSP). 28nm tech-nology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and Xpower Analyser. Vedic multiplier gains speed improvements by parallelizing the generation of partial prod-ucts with their concurrent summations. In this work, we are exploring the feasibility of Vedic multiplier in Data Encryption Algorithm, DSP, reliable system, multimedia and fault tolerant systems. In our work, we are using 11 different IO standards from HSTL (High Speed Transistor Logic) and LVCMOS (Low Voltage Comple-mentary Metal Oxide Semiconductor) family. IO standards are used to match the impedance of transmission line, input/output port and device. The energy-efficient multipliers play a significant role in portable computing and communication systems also. Here we are using Field Programmable Gate Array (FPGA) in order to re-duce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy efficient Vedic multiplier. There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7oC, 53.5oC, 40oC and 21oC respectively.
Keywords
Energy
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