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Sahoo, Bibhudutta
- A Novel Modulo (2n + 1) Multiplication Approach for IDEA Cipher
Authors
1 Department of Computer Sc. & Engineering, National Institute of Technology, Rourkela, Odisha, IN
2 Department of Computer Science & Engineering, National Institute of Technology, Rourkela, Odisha, IN
Source
Programmable Device Circuits and Systems, Vol 2, No 11 (2010), Pagination: 187-193Abstract
This paper covers the FPGA implementation of the International Data Encryption Algorithm (IDEA) using Very Large Scale Integrated Circuits Hardware Description Language (VHDL) with device as Vertex II Pro XC2VP30 using Xilinx – ISE 10.1. IDEA is very much fast and entirely based on internal group operations-XOR, modulo addition and modulo multiplication. So unlike other symmetric key block ciphers like AES or DES, there is no need for S-Boxes or P-Boxes in round operations. To use an encryption algorithm in real time applications like Cable TV, Video conferencing, the speed i.e. the data throughput rate needs to be high. The multiplication modulo (2n + 1) is the main module of this IDEA block cipher, as this module is highly computation intensive and consumes a lot of time. Due to regularity of IDEA, it has been implemented in hardware several times using different architectures. This paper mainly focuses on implementing a new algorithm and architecture for modulo (2n + 1) multiplication which takes the input in a diminished-1 form [2] and produces the product in the same form. This is a new modulo (2n + 1) approach for implementing IDEA in hardware. The proposed multiplier optimizes the time by producing n/2 partial products and handles zero values very efficiently. The performance of the proposed multiplier is analyzed in terms of time delay and circuit complexity and is compared with some existing schemes of diminished-1 modulo multipliers like Zimmerman [15], Sousa and Chaves [10] and Efstathiou [15][ 3].Keywords
Diminished-1Representation, IDEA Cipher, Hardware Implementations, Modulo Multiplier, Partial Products.
- Optimizing Power Consumption in Cloud Using Task Consolidation
Authors
1 Department of Computer Science & Engineering, NIT, Rourkela, Odisha, IN
2 Computer Science and Engineering Department, NIT, Rourkela’s, IN
3 Department of Computer Science & Engineering, National Institute of Technology, Rourkela, Odisha, IN
Source
Networking and Communication Engineering, Vol 7, No 4 (2015), Pagination: 155-162Abstract
Energy consumed by modern computer systems, particularly by servers in a Cloud has almost reached at an unacceptable level. Also the energy consumed due to underutilization of resource accounts almost 60% of the energy consumed at peak load [6]. Therefore, task consolidation plays an important role in cloud computing, which map users’ service requests to appropriate resources resulting in proper utilization of various cloud resources. Task Consolidation results in significant improvements in energy savings and also enhances overall performance of cloud computing. In our approach, we present an energy aware model for task consolidation problem. The model includes description of physical hosts, virtual machines and service requests (tasks) submitted by users. For the proposed model, an Energy Aware Task Consolidation (EATC) algorithm is developed. ETC (Expected Time to Compute) matrix is used to generate heterogeneity in the cloud system. Performance is evaluated against another heuristic and the results show significant improvement in energy savings.