Informatics Publishing Limited

B. Lakshmi ¹, R. Arunprasath ²

Affiliations
1 Department of VLSI, Anna University, Regional Office, Madurai, IN
2 Anna University Regional Office, Madurai, IN

Abstract

To prevent soft errors from causing data corruption, memories are typically protected with error correction codes. An advanced error correction codes are used when an additional protection is needed. The majority logic decoder/detector codes are used for memory application because of correcting large number of soft errors, less decoding time, area consumption. The EG-LDPC codes are suitable for error correction using majority logic decoder/detector. Because the EG-LDPC codes are small, powerful and easily implemented in terms of decoding latency and complexity and this design achieving very high data rate while minimizing complexity. The proposed improved majority logic decoder/detector to perform silent data error detection in simple way using additional error detection technique and also reducing the area of the majority gate using sorting network. Hence the decoding process uses less number of cycles, reduces the area and also reducing the power consumption.

Keywords

EG-LDPC Code, Error Correction Codes, Majoritylogic Decoding, Memory.

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K. R. Vishnupriya ¹, B. Lakshmi ², R. Srinivasan ²

Affiliations
1 Department of Information Technology in SSN College of Engineering, Kalavakkam – 603 110, Chennai, Tamilnadu, IN
2 Department of Information Technology in SSN College of Engineering, Kalavakkam – 603 110, Chennai, Tamilnadu, IN

Abstract

This paper investigates the effect of process variations on unity gain frequency (ft) in 30 nm gate length FinFET by performing extensive TCAD simulations. Six different geometrical parameters, channel doping, source/drain doping and gate electrode work function are studied for their sensitivity on ft. It is found that ft is more sensitive to gate length, underlap, gate-oxide thickness and SD doping and less sensitive to source/drain width and length, and work function variations.

Keywords

f_t, FinFET, Scaling, Process Variations.

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A. Vedamurthachar ¹, B. Lakshmi ¹, Swathi Reddy ¹, Anita R. Bijoor ², Vaishali Agte ³

Affiliations
1 Ved Vignan Maha Vidya Peeth, Udayapura, Bangalore, IN
2 Department of Biochemistry, St, John Medical College, Bangalore, IN
3 Agharkar Research Institute, Pune, IN

Abstract

Sudarshan Kriya Yoga (CSKYJ) practice designed to minimize stresses in daily life and improve the health status. The aim of this study was to assess the positive impact of sudarshan kriya program on healthy adult volunteers. We conducted an open trial on 102 apparently healthy adult volunteers to evaluate the effect of SKY practice on health, personal growth initiative and quality of life. Participants were given 6-day SKY training in three-four hour daily sessions. Main outcome measures were biochemical measures (Fasting Glucose Total cholesterol HDL, LDL, Triglycerides), PGIS for personal growth and WHOQOL Bref for quality-of-life measures (physical, emotional, social and spiritual well-being). Pre scores were compared with post scores to assess the impact of the SKY program. The scores and other measures were recorded at the beginning and end of the training period. Practice of SKY resulted in significant increase in PGIS score (t=-7.79, P < 0.001), four domain and total scores of QOL (physical health scores (t=-6.02, P < 0.001), psychological health (t=-9.43, P < 0.001), social relationships (t=-5.92, P < 0.001), environment (t=-6.03, P < 0.001).There was also a reduction in triglycerides (t=6.63, P < 0.001), fasting cholesterol (t=3.37, P = 0.013), LDL (t=2.17, P = 0.002), VLDL (t=6.67, P < 0.001)after the yoga workshop. A marginal increase was observed in fasting glucose (P = 0.009) and HDL (t=-2.51, P = 0.008). This pilot study suggests that a yoga-based wellness program is effective in creating both positive frame of mind and health and wellness for the population.

Keywords

Sudarshan Kriya, Health, Quality of Life.

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B. Lakshmi ¹, E. Kirubakaran ², T. N. Prabakar ³

Affiliations
1 Jayaram College of Engineering and Technology, Tiruchirappalli, IN
2 Bharat Heavy Electricals Ltd, Tiruchirappalli, IN
3 Saranathan College of Engineering, Tiruchirappalli, IN

Abstract

In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS - II processor (a virtual microcontroller which is brought out from Altera FPGA) that communicates with the keys to the personal computer through JTAG (Joint Test Action Group) communication and the computer is used to perform encryption (or decryption). In this case the FPGA serves as hardware key (dongle) for data encryption (or decryption).

Keywords

Encryption, Decryption, Real Time Systems, Time Based Key, Brute Force Attack, Cryptanalysis, FPGA.

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