Informatics Publishing Limited

C. Uthaya Kumar ¹, B. Justus Rabi ²

Affiliations
1 Karpagam University, Coimbatore - 641021, Tamil Nadu, IN
2 Shri Andal Alagar College of Engineering, Chennai - 603111, Tamil Nadu, IN

Abstract

The aim of the current research work is to improve the architectural performances of digital filter. An efficient Multiplication and Accumulation (MAC) unit called “Russian Peasant Multiplier” is modified in this research work to alleviate the filter architecture. In proposed methods, switching activities of multiplier values has been validated by using only left shifters only, where as traditional Russian peasant multiplication has two shifters namely left and right respectively for validating multiplier values. Reduced Wallace Tree Generation (RWTG) method has been used to re-arrange the partial product results. Further Modified Square Root Carry Select Adder (MSQRTCSLA) has been incorporated into RWTG for performing accumulation operation of Multiplication. Proposed digital FIR Filter offers 45.61% improvements in hardware slices, 42.02% improvements in Slice Flip-flops, 22.36 improvements in sequential delay, 1.56% improvements in minimum input arrival time before clock, 0.86% improvements in maximum output required time after clock, 19.52% improvements in dynamic power and 18.32% improvements in total power consumption than traditional Russian peasant multiplication based digital FIR filter. In future, proposed MAC based FIR filter architecture will be absolutely suited to Software Defined Radio (SDR) and Orthogonal Frequency Division Multiplexing (OFDM) based data communication applications for improving hardware speed and power consumptions.

Keywords

Reduced Full Adder, Reduced Gate Level Logic, Reduced Half Adder, VLSI based filter design, Wallace Tree Generation

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K. Malathy ¹, B. Justus Rabi ²

Affiliations
1 Karpagam University, Coimbatore - 641021, Tamil Nadu, IN
2 Shri Andal Alagar College of Engineering, Chennai - 600026, Tamil Nadu, IN

Abstract

The aim is to design a new architecture called "Novel Radix-2 Single path Delay Commutator (R2SDC)" for improving the architectural performances of Fast Fourier Transformation (FFT) technique. In proposed new architecture, only commutator structures and complex multipliers are used to convert the time domain signals into frequency domain signals. In order to match the frequency response, delay elements are used appropriately. Traditional pipelined architectures have multiple complex multiplication units for performing frequency transformation techniques. But, proposed R2SDC structure has single complex multiplication unit per stage. Data flow structures of R2SDC architecture has been designed through Very Large Scale Integration (VLSI) System design environment. Proposed novel architecture called R2SDC FFT offers 21.4% improvements in hardware slices, 26.76% improvements in Look Up Tables (LUTs), 23.49% improvements in maximum output required time after clock and 31.88% improvements in power consumptions than traditional pipelined Radix-2 Single path Delay Feedback (R2SDF) FFT architecture. Also proposed architecture offers 4.61% improvements in hardware slices, 6.52% improvements in LUTs and 10.10% improvements in power consumption than combined SDC-SDF FFT architecture. In future, proposed R2DSC FFT architecture will be useful in Orthogonal Frequency Division Multiplexing (OFDM) architecture for estimating the frequency response of digital signals. It will be useful in large distance communications based applications

Keywords

Analog to Digital Converter, Combined Single path Delay Feedback –Single path Delay Commutator, Orthogonal Frequency Division Multiplexing, Radix-2 Single path Delay Commutator, Very Large Scale Integration

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