Informatics Publishing Limited

Gaurav Gupta ¹, Amit Mahesh Joshi ², Kanika Sharma ¹

Affiliations
1 Department of Electronics and Communication Engineering, National Institute of Technical Teachers Training and Research, Chandigar, IN
2 Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, IN

Abstract

The expansion of technology has made several simple ways to manipulate the original content. This has brought the concern for security of the content which is easily available in open network. Digital watermarking is the most suitable solution for the defined issue. Digital watermarking is the art of inserting the logo into multimedia object to have proof of ownership whenever it is required. The proposed algorithm is useful in authorized distribution and ownership verification. The algorithm uses the concept of AC prediction using DCT to embed the watermark in the image. The algorithm has excellent robustness against all the attacks and outperforms the similar work with admirable performance in terms of Normalized Correlation (NC), Peak Signal to Noise Ratio (PSNR) and Tamper Assessment Function (TAF).

Keywords

Blind Retrieval, Digital Rights Management, Error Correction, Invisibility, Robustness.

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Balotia Suresh Kumar ¹, Amit Mahesh Joshi ¹

Affiliations
1 Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, IN

Abstract

Data stability is one of the important parameter of SRAM with scaling of CMOS technology. However the move to nanometer technology not only nodes has increased, but the variability in device characteristics has also increased due to large process variations. Static random access memory (SRAM) is a popular component which is used in modern microprocessors and occupies a considerable chip area. It is useful to store the data as well as read and write operation. The performance of SRAM circuit is measured with data stability and read-write SNM (Static Noise Margin). A novel power gated SRAM cell is presented in this paper with enhanced data stability and reduced leakage power. The data becomes completely isolated form bit line during read operation in new power gated SRAM. The SNM of the new power gated cell is thereby increased by 2 times in comparison to a conventional six transistor (6T) SRAM cell. The paper also covers the comparative analysis and simulation of both SRAM cell on the basis of Read Noise Margin and Write Noise Margin. The novel power gated SRAM cell has larger read and write SNM as compared to conventional 6T SRAM cell at different technologies. All results are carried out on 45nm, 32nm and 22nm CMOS technology using HSPICE simulation tool.

Keywords

Cell Ratio, Power Gated, Read Margin, Static Noise Margin, Write Margin.

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