Informatics Publishing Limited

Abstract

Now a day’s flip-flops are the key building blocks of VLSI circuits, since they have a substantial impact on the performance energy at the chip level.  A low-power Flip-Flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock based on a signal feed-through scheme is presented. The proposed design is to achieve better speed, less area and power performance. In the design, universal elements are used instead of universal gates to reduce number of transistors count. Despite its circuit simplicity, no internal nodes are left floating during the operation to avoid leakage power consumption. By these a virtual drain supply (VDD) design technique, which facilitates a faster state transition in the slave part, is to enhance performance time. The overall power consumption is compared for each case in different technologies. The average power, maximum power can be calculated with =1.8V. The simulation is performed using TANNER V13.0.

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