International Journal of Science, Engineering and Computer Technology

Suman Gill ¹, Munna Dev ¹, Rajesh Kumar ¹

Affiliations
1 Department of Electronics and Communication Engineering, Manav Institute of Technology & Management, Jevra, Hisar, Haryana, IN

Abstract

The proposed method uses the built-in scan-chains in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. The use of these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. Dual threshold voltage (DVT) domino logic utilizes dual Vt's to provide the performance equivalent of a purely low Vtdesign with the standby leakage characteristic of a purely high Vtimplementation. DVT domino logic is an attractive circuit style compared to other dual Vttechniques because there are no performance penalties, no difficult transistor sizing issues, and all gates (not just non-critical ones) can be compensated.

Keywords

Power Dissipation, Cmos Devices, Dual-Threshold Voltage Techniques.

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Suman Gill ¹, Munna Devi ¹, Rajesh Kumar ¹

Affiliations
1 Department of Electronics and Communication Engineering, Manav Institute of Technology and Management, Jevra, Hisar, Haryana, IN

Abstract

As power is always a critical issue in digital integrated circuits. For minimization of this power various methods using dynamic threshold voltage MOSFET for ultra-low power applications [1]. Chandel has done comparative analysis for 1 and 2 bit binary operand adder circuits [4]. Again, chandel has implemented low power technique in CMOS based flip-flop circuit [8]. In the various leakage power components is modelled and analysed [9]. And same model is utilized in various circuits for estimation of various parameters. Gate diffusion input technique has been used for designing various arithmetic circuits [13, 14]. An overview on low power design technique is detailed and leakage control transistor technique and multi-threshold technique implementation is detailed [16]. Optimum power concept is introduced is used in various digital circuits [15]. A new circuit technique is proposed in this research work MTCMOS using bulk bias. In order to maintain performance and a large enough gate overdrive, it is necessary to scale threshold voltages. By scaling the supply voltage and the threshold voltage, the increase in subthreshold leakage power is small as compared to the quadratic reduction in the dynamic power supply.

Keywords

CMOS Digital Integrated Circuits, MTCMOS.

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