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Chandel, Pallavi
- Speed Efficient FPGA Based Direct form Fir Interpolator
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1 Fellow, LCET, Katani Kalan, Ludhiana, Punjab, IN
2 Assistant Professor, LCET, Katani Kalan, Ludhiana, Punjab, IN
1 Fellow, LCET, Katani Kalan, Ludhiana, Punjab, IN
2 Assistant Professor, LCET, Katani Kalan, Ludhiana, Punjab, IN
Source
Indian Journal of Applied Engineering Research, Vol 1, No 1 (2013), Pagination: 73-82Abstract
In this paper high speed and area efficient interpolator has been designed and simulated for wireless communication. Interpolator is implemented by using MAC algorithem.This method is useful to enhance the performance in terms of speed and area. The proposed interpolator has been designed by using Half band Transposed FIR Structure with Matlab simulated with Modelsim tools(XST) and implemented on Spartan-3E device.The proposed model has shown maximum operating frequency of 64.338MHZ as compare to existing MAC based interpolator.Keywords
DSP, Interpolator, MAC, FIRReferences
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