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Awadalla, Medhat
- Design of a Gray Encoder and Counter Using D-FFs and MUXs
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Authors
Affiliations
1 Department of Electrical and Computer Engineering, College of Engineering, Sultan Qaboos University, OM
2 Department of Communications and Computers, Helwan University, EG
1 Department of Electrical and Computer Engineering, College of Engineering, Sultan Qaboos University, OM
2 Department of Communications and Computers, Helwan University, EG
Source
Oriental Journal of Computer Science and Technology, Vol 10, No 3 (2017), Pagination: 539-548Abstract
This paper proposes a novel design for Binary to Gray code encoders and/or counters using multiplexers and flip-flops. The proposed design are modular based, whereby other stages can be added as per the requirement of the desired applications. Moreover, the external clock timing signal drives only the first stage, while all remaining stages are linked to the outputs from preceding stages. The successive stages transitions at half the rate of the preceding stage thereby, makes the design power efficient since the dissipated power is quadratic frequency dependent. The proposed design can be modified to increase the counters duration or increase the counters resolution according to the applications need. Increasing the Gray counters time span by powers of two simply necessitates augmenting the design by more stages, while maintaining a constant clock rate. On the other hand, doubling the time resolution of the Gray counter over a constant time span can be achieved by adding another stage while subsequently doubling the clock rate.Keywords
Gray Code, Reflected Binary Code, Encoder, Counter, D-FF.Full Text
References
- F. Gray, “Pulse code communication,” United States Patent Number 2,632,058, March 17, 1953.
- I. Flores, “Reflected number systems,” IRE Trans. Electronics & Computer, vol.5(2), pp.79-82, June 1956
- F. G. Heath, “Origins of the binary code,” Scientific American, vol. 227(2), p.76, August 1972.
- A. Ahmad, and A. Al-Maashri, “Design and analysis of newly innovated set of binary code-words of unitary Hamming distance,” Proceedings IEEE international conference on communication, computer and power (ICCCP’07), Muscat, Oman, pp.162-168, Feb. 19-21, 2007
- T. N. Kwan, S. Chen, F. Boussaid and A. Bermak, “Compact Gray-code counter/memory circuits for spiking pixels,” Proceedings Fourth IEEE International Symposium on Electronic Design, Test and Applications-DELTA 2008, Hong Kong, SAR, China, pp.506-511, 23-25 January 2008.
- S.V. Yarmolik and V.N. Yarmolik, “Modified Gray and counter sequences for memory test address generation,” Proceedings of the International Conference, Mixed Design of Integrated Circuits and System, (MIXDES 2006), pp.572-576, 2006.
- H. Mehta, R. M. Owens and M. J. Irwin, “Some issues in Gray code addressing,” Proceedings of the 6th Great Lakes Symposium on VLSI, pp 178-181, 22-23 Mar 1996.
- C. L. Su, C. Y. Tsui and A. Despain, “Saving power in the control path of embedded processors,” Proceedings of IEEE Design and Test of Computers, pp. 24-31, 1994.
- C. L. Su,M. Alvinand A. Despain, “Cache design trade-offs for power and performance optimization: A Case Study. ISLPD, pp. 63-68,1995.
- A. Maheshwari, W. Burleson and T. Russell, “Trading off reliability and power consumption in ultra-low power systems,”Proceedings International Symposium on Quality Electronic Design, pp. 361-366, 2002.
- R.Hakenes andY. A.Manoli, “Segmented gray code for low-power microcontroller address buses,” Proceedings of 25th EUROMICRO Conference, .Vol.1, pp. 240-243, 1999.
- A. Ahmad, D. Ruelens, M. H. A. Awadalla and S. Ahmad, “An optimized technique for machine state reduction,” The Third International Conference on Numerical Analysis and Optimization NAOiii-2014, held at Sultan Qaboos University, Oman, January 5-9, 2014, Book Program & Abstracts, p. 36.
- S. Kundu, K.S.Krishna and S. Chattopadhyay, “Test pattern selection and customization targeting reduced dynamic and leakage power consumption,” Proceedings Asian Test Symposium., CD-ROM Proceedings, November 2009.
- S. Kundu and S. Chattopadhyay, “Scan-chain masking technique for low power circuit testing,” Proceeding of ASQED 2009, pp. 183-188
- M.V. Rao, N. S. Sravaniand S. P. V. A. Brahmanandam, “Self-test techniques in SoC for low power consumption,” Int. J. Comp. Tech. Appl., vol.2(6), pp.1903-1906, 2011
- N. Gupta, “Reduce SoC power use without high level EDA tools,” EE Times-Asia, pp. 1-4, 2013.
- A.Ahmad, “Another Perspective in Generation and using of Gray Code-words”, Journal of Electrical Engineering, IEEE Malaysia, (ELEKTRIKA), vol.9(2), pp.49-55, 2007.
- A. Ahmad, and M. M. Bait Suwailam, “Design of an efficient and less memory requiring algorithmic procedure for computing Gray codes,” Proceedings IEEE international conference on communication, computer and power (.ICCCP’07), Muscat, Oman, pp.172-176, Feb. 19-21, 2007.
- A. Ahmadand M. M. Bait Suwailam, “A less complex algorithmic procedure for computing Gray codes,” The Journal of Engineering Research, vol.6(2), pp.12-19, 2009.
- A. Ahmad and F. Bait-Shiginah, “A nonconventional approach to generating efficient binary Gray code sequences,” IEEE Potentials, vol.31(3), pp.16-19, 2012.
- Wikipedia—rotary encoder [Online]. Available at:http://en.wikipedia.org/wiki/Rotary_encoder
- C. Burch, C, “Logisim: A graphical system for logic circuit design and simulation”, Journal of Educational and Resources in Computing, vol. 2(1), pp. 5-16, 2002.