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Bhagyalakshmi, V
- A BDD-based Design of An Area-Power Efficient Asynchronous Adder
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1 Asst.Professor(EXTC), V.V.P.I.E.T, Solapur
2 H.O.D(EXTC),V.v.P.I.E.T,Solapur.
1 Asst.Professor(EXTC), V.V.P.I.E.T, Solapur
2 H.O.D(EXTC),V.v.P.I.E.T,Solapur.
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International Journal of Electronics and Communication Engineering, Vol 6, No 1 (2013), Pagination: 93-103Abstract
Asynchronous system design in recent years has reemerged as an important vehicle in the field of high performance, low power and secure computing. On the other hand Binary Decision Diagrams (BDDs) have found significant applications for many years in the design, synthesis, verification, and testing of VLSI circuits. In this paper we have presented the design of a hybrid Domino Pass Transistor Logic CMOS (PTL-CMOS) based 2-bit asynchronous adder, the PTL part of which is designed using the principles of BDD. Furthermore using this design as basic building block a 8-bit asynchronous adder has been implemented. The simulation results indicate a reduction in number of transistors over Minimal Energy Dual-bit Dynamic adder (MEDB) adder without any compromise in the delay. The circuit is simulated using Cadence tool, UMC 180nm, 1.5 technology.References
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