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Authors
Affiliations
1 Asst. Professor, Dept. of ECE, SRK Institute of technology, Enikepadu, Vijayawada-512108, Andhra Pradesh, IN
Source
International Journal of Electronics and Communication Engineering, Vol 6, No 1 (2013), Pagination: 9-16
Abstract
In this paper a simple method to improve the throughput of multipliers was presented. The method used is the double precision. In this method the operands of the multiplier will be made into narrow width operands. Hence the power dissipation and throughput of the multipliers will be improved. Here we will also describe how to apply this new method to the familiar multipliers such as Booth and Baugh-wooley. The proposed algorithm will be modeled using VHDL. Then the performance of these multipliers is compared with each other.
Keywords
Double Throughput, Reduced Power Consumption, Double Precision, Modified-booth, Baugh-wooley, Final Adder
References
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- A. D. Booth, “A signed binary multiplication technique,” Quarterly J.Mechan. Appl. Math., vol. 4, no. 2, pp. 236–240, 1951.
- H. Eriksson, P. Larsson-Edefors, M. Sheeran, M. Själander, D. Johansson, and M. Schölin, “Multiplier reduction tree with logarithmic logic depth and regular Connectivity,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2006, pp.4–8.
- C. R. Baugh and B. A. Wooley, “A two’s complement parallel array multiplication algorithm,” IEEE Trans. Comput., vol. 22, pp. 1045–1047, Dec. 1973
- M. Sjalander, H. Eriksson, and P. Larsson-Edefors, “An efficient twin-precision multiplier,” in Proc. IEEE Int. Conf. Comput. Des. Oct.2004,pp. 30-33.
