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David Solomon Raj, K.
- Sleepy Keeper Approach for Power Performance Tuning in VLSI Design
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Authors
Affiliations
1 Department of Electronics and Communication Andhra Loyola Institute of Technology
2 Department of electronics and communication S.R.K. Institute of Technology
3 Department of Avionics, JNTU Kakinada
1 Department of Electronics and Communication Andhra Loyola Institute of Technology
2 Department of electronics and communication S.R.K. Institute of Technology
3 Department of Avionics, JNTU Kakinada
Source
International Journal of Electronics and Communication Engineering, Vol 6, No 1 (2013), Pagination: 17-28Abstract
There are several techniques that reduce leakage power in efficient way but the disadvantage of each technique limits the application of each technique. In this paper sleepy keeper approach is introduced to reduce the power dissipation of the circuit in idle state when its logic is not needed. The sleepy keeper approach uses traditional sleep transistors and two additional transistors which are driven by already calculated gate output. This saves the state during sleep mode. Multi threshold transistors are used in order to reduce subthreshold leakage power and also to increase the switching speed of the circuit.Keywords
Leakage Power, Subthreshold Leakage Currents, Sleep Mode, Idle ModeReferences
- R. Ronen et al., “Coming challenges in microarchitecture and architecture,” Proc. IEEE, vol. 89, pp. 325–339, Mar. 2001.
- S. Borkar, “Obeying moore’s law beyond 0.18 micron,” in Proc. IEEE Int. ASIC/SOC Conf., Sept. 2000, pp. 26–31.
- M. T. Bohr, “Nanotechnology goals and challenges for electronic applications,”IEEE Trans. Nanotechnol., vol. 1, pp. 56–62, Mar. 2002.
- J. Kao, “Dual threshold voltage domino logic,” in Proc. Eur. Solid-State Circuits Conf., Sept. 1999, pp. 118–121
- K. Zhang, U. Bhattacharya, C. Zhanping, F. Hamzaoglu, D. Murray,N. Vallepalli, W. Yih, B. Zheng, and M. Bohr, “SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction,”IEEE Journal of Solid State Circuits, vol. 40, no. 4, pp. 895–901, April 2005.
- K.-S. Min, H. Kawaguchi and T. Sakurai, “Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller:
- J. Park, “Sleepy Stack: a New Approach to Low Power VLSI and Memory,” Ph.D. Dissertation, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005. [Online]. Available http://etd.gatech.edu/theses