Refine your search
Collections
Co-Authors
Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Anand, A.
- A Novel Decoding Approach for Non-Binary LDPC Codes in Finite Fields
Abstract Views :256 |
PDF Views:0
Authors
A. Anand
1,
P. Senthilkumar
1
Affiliations
1 Saveetha Engineering College, Chennai, IN
1 Saveetha Engineering College, Chennai, IN
Source
International Journal of Electronics and Communication Engineering, Vol 5, No 2 (2012), Pagination: 133-141Abstract
In this paper we propose an integrated version of EMS (Extended Min-Sum) and layeredturbo decoding in Low density Parity Check Codes. Algorithmic complexity and memory problems are the major problem faced in NB-LDPC. This can be reduced by EMS algorithm under logarithm domain in the order of (nm log 2 nm). Speed is increased by using layered turbo scheduled decoding algorithm. Efficient implementation of non-binary LDPC decoders is a progressing field which is updated currently. This paper is based on (1) the hardware implementation costs for NB-LDPC decoders with Galois field (8,16,128,256) on FPGA and (2) To set the noise threshold very close to the theoretical maximum (Shannon Limit).Keywords
NB-LDPC, EMS, Layered Turbo Scheduled Decoding Algorithm, BP
References
- Timo Lehnigk-Emden, Norbert Wehn “Complexity Evaluation of Non-binary Galois Field LDPC Code Decoders” in 2010 6th International Symposium on Turbo Codes& Iterative Information Processing,
- C. Spagnol, W. Marnane, and E. Popovici, “FPGA Implementations of LDPC over GF(2m) Decoders,” in Proc. IEEE Workshop on Signal Processing Systems, Oct. 2007, pp. 273-278.
- A. Voicila, F. Verdier, D. Declercq, M. Fossorier, and P. Urard, “Architecture of a low-complexity non-binary LDPC decoder for high order fields,” in Proc. International Symposium on Communications and Information Technologies ISCIT '07, Oct. 2007, pp. 1201-1206.
- A. Voicila, D. Declereq, F. Verdier, M. Fossorier, and P. Urard, “LowComplexity, Low-Memory EMS Algorithm for Non-Binary LDPC Codes” in Proc. IEEE International Conference on Communications ICC '07, Jun. 2007, pp. 6371-676.
- M. Karkooti, P. Radosavljevic, and J. R. Cavallaro, “Configurable, High Throughput, Irregular LDPC Decoder Architecture:Tradeoff Analysis and Implementation,” IEEE 17th International Conference on Application specific Systems, Architectures and Processors, pp. 360–367, Sep. 2006
- M. M. Mansour and N. R. Shanbhag, “High-throughput LDPC decoders,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, pp. 976–996, Dec. 2003.
- R. Gallager, “Low-density parity-check codes,” IEEE Transactions on Information Theory, vol. 8, pp. 21–28, Jan. 1962.
- J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier and X. Hu, “Reduced- Complexity Decoding of LDPC Codes,” IEEE Transactions on Communications, vol. 53, pp. 1232–1232, 2005.