International Journal of Scientific Engineering and Technology

Yash Agrawal ¹, Rohit Dhiman ¹, Rajeevan Chandel ¹

Affiliations
1 Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur-177 005, Himachal Pradesh, IN

Abstract

In deep submicron VLSI circuits, interconnect delays dominate MOSFET gate delays. Conventional buffer insertion method reduces delays at the cost of valuable chip area. Consequently, alternative methods are essential. Current mode interconnects have lesser delay than voltage mode circuits and also consume lesser chip area. In the present work, superiority of current mode over voltage mode interconnects is analyzed. The simulative analysis is carried out using Tanner EDA tools.

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Yash Agrawal ¹, Rohit Dhiman ¹, Rajeevan Chandel ¹

Affiliations
1 Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur-177 005 HP, IN

Abstract

A receiver subsystem for current mode interconnects is presented in the present paper. It is shown that current mode interconnects shows better performance compared to voltage mode interconnect circuits. The current mode interconnect system using proposed receiver subsystem shows about 15% lesser latency and 40% increased throughput. Effect of voltage scaling on power dissipation for current mode (CM) and voltage mode (VM) has been analyzed. Current mode interconnects shows lesser power dissipation compared to voltage mode circuits. Analysis has been carried out using SPICE in 0.18 μm technology.

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