Design of Low Voltage and Low Power D-Flip Flop

This paper presents a novel D flip-flop for low voltage operation with improved speed using SPICE simulation, it takes advantage of a dynamic threshold voltage using DTMOS for ultra-low voltage operation and a negative differential resistance storage using Bistable Gated Bipolar Device (BGB). DTMOS provides low power consumption and BGB provides high speed because of less capacitance. So we have taken advantages of both the DTMOS and BGB device to make the D-Flip Flop for low power operation with high speed and low leakage current. Leakage is further reduced by addition of two sleep transistors.