New Generation Fast and Optimized Modulo (2n+1) Multiplier for IDEA

International data encryption algorithm, a federal information processing standard is an approved cryptographic algorithm that can be used to protect electronic data. This paper present the IDEA algorithm with regard to FPGA and the very high speed integrated circuit hardware description language. Synthesizing and implementation of the VHDL code carried out on Xilinx-project navigator, ISE suite. In this paper an efficient hardware design of the IDEA using modulo (2ⁿ+1) multiplier as the basic module proposed for faster, smaller and low power IDEA hardware circuit. Experimental measurement result show that the proposed design is faster and smaller and also consume less power than similar hardware implementation making it a viable option for efficient This paper talks of IDEA 64 bit plain text, 128 bit key and 64 bit cipher text.