International Journal of Scientific Engineering and Technology

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Area Efficient 4-Input Decimal Adder Using CSA and CLA


Affiliations
1 Department of Electronics and Communication Engineering, Suresh Gyan Vihar University, Jaipur, Rajasthan, India
 

In Today we need exact results in our computation commercial application decimal arithmetic in their computation program it takes lot of time by software support we get results but system become slower so in this paper an area efficient 4-input decimal adder using CSA and CLA is proposed to give hardware support for decimal arithmetic synthesis shows that it reduces on chip area and consume less power with same propagation delay then previously proposed adder. It could perform complex addition as per our requirement.

Keywords

VLSI Design, Carry Look Ahead Adder, Carry Save Adder, Parallel Prefix Adder, Decimal Addition, Computer Arithmetic.
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  • Area Efficient 4-Input Decimal Adder Using CSA and CLA

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Authors

Shailesh Siddha
Department of Electronics and Communication Engineering, Suresh Gyan Vihar University, Jaipur, Rajasthan, India

Abstract


In Today we need exact results in our computation commercial application decimal arithmetic in their computation program it takes lot of time by software support we get results but system become slower so in this paper an area efficient 4-input decimal adder using CSA and CLA is proposed to give hardware support for decimal arithmetic synthesis shows that it reduces on chip area and consume less power with same propagation delay then previously proposed adder. It could perform complex addition as per our requirement.

Keywords


VLSI Design, Carry Look Ahead Adder, Carry Save Adder, Parallel Prefix Adder, Decimal Addition, Computer Arithmetic.