New Approach to Reduce Energy Consumption in Six Transistors SRAM

This paper presents the technique used to reduce the power dissipation in 6T SRAM. Normally there is a power loss in charging and discharging the bit line during reading and writing. This power loss is drastically reduced with the use of additional adiabatic circuit. Simulation of the circuit is done using HSPICE in 65nm technology. This circuit also preserve power during writing phase also.