ICTACT Journal on Microelectronics

Vivek Harshey ¹, S. K. Bansal ²

Affiliations
1 Department of Electronics and Communication Engineering, Sant Longowal Institute of Engineering and Technology, IN
2 Department of Electrical and Instrumentation Engineering, Sant Longowal Institute of Engineering and Technology, IN

Abstract

In deep sub-micron memories like DRAM and SRAM, faithful sensing of bit line voltages is becoming very challenging as transistor characteristics mismatch caused by intrinsic variations in manufacturing processes has posed a grave challenge leading to failures of circuits and reductions in yield. This paper addressed these issues and applied a compensation scheme to various schematics of sense amplifiers, which have resulted in a high tolerance to process-induced variations. The schematics, designed with DGFinFET, utilize an enhanced self-compensation technique to surmount disparities in physical transistor characteristics. The recreations of transistor mismatch (threshold voltage, Vt) using the Monte-Carlo technique show that the proposed CCLSA schematic performs correctly even for severe Vt mismatch of 40-50mV. These results are compared with corresponding circuits reported in the literature for the speed, area, and yield. This design also offers up to 20-30 % higher yield compared to its uncompensated counterpart and has a reduced penalty for the complexity of circuit and performance. These circuits are easily implementable at 45nm and 32nm technology nodes.

Keywords

Compensation, Process Variations, DRAM, FinFET Sense Amplifier, Robustness.

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Vivek Harshey ¹, Pankaj Kumar Das ², Shivani Sharma ³

Affiliations
1 Department of Electronics and Communication Engineering, IN
2 Department of Electronics and Communication Engineering, Sant Longowal Institute of Engineering and Technology, IN
3 Department of Electronics and Communication Engineering, Dr. B.R. Ambedkar National Institute of Technology, IN

Abstract

At the current deep submicron and nanometer level, the leakage power is becoming the major contributor to overall power consumption in modern VLSI circuits. This research paper presents a novel approach to reducing leakage power by inserting two leakage transistors in the middle of pull-down and pull-up paths. Out of these two leakage transistors, one is the PMOS transistor, and another one is the NMOS transistor. This research work presents a dynamic CMOS inverter and 6T SRAM cell with and without transmission gate (TG) to reduce leakage power using the LECTOR and LECTOR-B techniques. The Cadence Virtuoso simulation tool is used to presents the results in terms of static power. Using the 45-nm technology node, the performance in terms of static power is analyzed. It is observed that using LECTOR and LECTOR-B techniques, the overall reduction in static power is 26% and 20%, respectively, compared to the conventional design for SRAM cell. Similar improvements are also noted for dynamic CMOS inverter and TG SRAM cell.

Keywords

Dynamic CMOS Inverter, SRAM Cell, Leakage Power, LECTOR, LECTOR-B Technique

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