Refine your search
Collections
Co-Authors
Journals
Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Abe, Susan
- Gate Engineering of Double Gate In0.53Ga0.47As Tunnel FET
Abstract Views :225 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 1, No 3 (2015), Pagination: 91-95Abstract
Increased power-dissipation in upcoming generation digital systems are limited by supply voltage reductions. For such systems, transistors with lower Subthreshold Slopes are needed. Tunnel Field Effect Transistors (TFET), which works on the principle of band-to-band tunnelling, are supposed to be the possible solution for this problem. TFETs ON-current (ION) is usually very low, with the use of semiconductors with indirect and large bandgap, and high effective mass as silicon, where tunnelling probability is depressed. One solution to this problem is the use of III-V semiconductors like InAs, GaSb, GaAsSb, InxGa1-xAs etc. and structure of gate is another important factor. Double gate instead of a single gate structure will provide improvement in ION. Work function of the gate material also has a great impact. In this paper, a study of the impact of In0.53Ga0.47As channel material, gate structure, work function and high-k dielectric for gate for TFET using Cogenda VTCAD is presented.Keywords
Band to Band Tunnelling, Double Gate TFET, III-V Semiconductors, High-k Dielectric.
References
- R.H. Dennard, F.H. Gaenesslen, H.N. Yu, V.L. Rideout, E. Bassous, A.R. Le Blanc, “Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions”, IEEE Journal Solid State Circuits, Vol. 9, No. 5, pp. 256-268, 1974.
- Woo Young Choi, Byung - Gook Park, Jong Duk Lee and Tsu - Jae King Liu, “Tunneling Field Effect Transistor (TFETs) with Subthreshold Swing (SS) Less Than 60 mV/dec”, IEEE Electron Device Letters, Vol. 28, No. 8, pp 743-745, 2007.
- William M. Reddick and Gehan A. J. Amaratunga, “Silicon surface tunnel transistor”, Applied Physics Letters, Vol. 67, No. 4, pp. 494-496, 1995.
- Simon M. Sze and Kwok K. Ng, “Physics of Semiconductor Device”, 3rd Edition, John Wiley & Sons, Inc., 2007.
- Alan Seabaugh, “The Tunneling Transistor”, IEEE Spectrum, 2013.
- J. Appenzeller, J. Knoch, M.T. Bjork, H. Riel, H. Schmid and W. Riess, “Towards Nanowire Electronics,” IEEE Transactions on Electron Devices, Vol. 55, No. 11, pp. 2827-2845, 2008.
- J. D. Meindl. “Low Power Microelectronics: Retrospect and Prospect”, Proceedings of the IEEE, Vol. 83, No. 4, pp. 619-635, 1995.
- G. A. M. Hurkx, D. B. M. Klaassen and M.P.G. Knuvers, “A New Recombination Model for Device Simulation including Tunneling”, IEEE Transactions on Electron Devices, Vol. 39, No. 2, pp. 331-338, 1992.
- Evan O. Kane, “Theory of Tunneling”, Journal of Applied Physics, Vol. 32, No. 1, pp. 83-91, 1961.
- Arathy Varghese, C. S. Praveen, Ancy P Mani and Ajith Ravindran, “InGaAs/ GaAsSb Heterojunction TFET”, IJCA Proceedings on International Conference on Emerging Trends in Technology and Applied Sciences, pp. 21-25, 2015.
- C. S. Praveen, Ancy P Mani, Arathy Varghese and Ajith Ravindran, “Analysis of GAA Tunnel FET using MATLAB”, IJCA Proceedings on International Conference on Emerging Trends in Technology and Applied Sciences, pp. 30 - 35, 2015.
- K. Boucart and A. M. Ionescu, “Double-Gate Tunnel FET With High-k Gate Dielectric”, IEEE Transactions on Electron Devices, Vol. 54, No. 7, pp. 1725-1733, 2007.
- Joachim Knoch, Siegfried Mantl and J. Appenzeller, “Impact of the Dimensionality on the Performance of Tunneling FETs: Bulk versus One-Dimensional Devices”, Solid-State Electronics, Vol. 51, No. 4, pp. 572-578, 2007.
- Ben G Streetman and Sanjay Banerjee, “Solid State Electronic Devices”, 5th edition, New Jersey Prentice Hall, 2000.
- E. Wigner and J. Bardeen, “Theory of the Work Functions of Monovalent Metals”, Physical Review Letters, Vol. 48, No. 1, 1995.
- K. Boucart and A. M. Ionescu, “Double Gate Tunnel FET with Ultrathin Silicon Body and High-k Dielectric”, Proceedings of the 36th European Solid State Device Research Conference, pp. 383-386, 2006.