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Kerur, S.S.
- Architectural Design And Optimization Of Distributed Arithmetic Based 2-d Discrete Cosine Transform
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, SDM College of Engineering and Technology, IN
1 Department of Electronics and Communication Engineering, SDM College of Engineering and Technology, IN
Source
ICTACT Journal on Microelectronics, Vol 8, No 1 (2022), Pagination: 1275-1282Abstract
DCT is immensely used in Multimedia applications because it provides high energy compaction. The proposed architectural design of 1D-DCT employs an efficient computational technique, Distributed arithmetic and is synthesized using front end VLSI technique. The motive of utilising Distributed arithmetic is to have multiplier-less architecture that reduces the Area-delay product in comparison to the multiplier-based design by retaining the same structural regularities. The symmetric property of the DCT kernel matrix is applied to develop the proposed architecture which reduces the requirements of a number of multiplications by almost 50%. The 1D-DCT architecture is extended to 2D-DCT using only N 1D-DCT modules, while the conventional row-column decomposition method requires 2N 1D-DCT modules. The proposed 2D-DCT architecture is designed and implemented on a 65nm LX110T device of Vertex-5 FPGA and its performance evaluation is carried out. The debug and verification process has been carried out using the Virtual input-output technique. The results show improvement in delay and area consumption in contrast with existing models.Keywords
Dimensional Discrete cosine transform (1D-DCT), Distributed arithmetic (DA), Multiply and accumulate (MAC), Field programmable gate array (FPGA)
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