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Jayasri, S.
- Error Compensation Technique for 90nm CMOS Fixed-Width and Area Efficient Booth Encoding Multiplier
Abstract Views :144 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Sri Shakthi Institute of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
3 Nano Electronics and Integration Division, IRRD Automatons, IN
1 Department of Electronics and Communication Engineering, Sri Shakthi Institute of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
3 Nano Electronics and Integration Division, IRRD Automatons, IN
Source
ICTACT Journal on Microelectronics, Vol 5, No 3 (2019), Pagination: 820-824Abstract
An area efficient, fixed width multiplier using booth encoding is done in this work. The work is further extended to accommodate the error correction feature. As in many signal processing products fast and efficient processing elements are required, the demand increases day by day. This work is one such finding to meet the standard of today’s contemporary technology. The proposed methodology suits well for the discrete cosine transform application. A new multiplier architecture using booth encoding is done. The architecture includes a tree based carry save reduction unit with parallel prefix adder and the compensation circuit. The work is carried out in 180nm technology using predictive technology models. The circuits are implemented using SPICE models and the results are obtained. For equal probability the inputs of different blocks are kept ‘1’ or ‘0’ in equal numbers. The frequency of operation is 100MHz. The proposed design will be compared with the existing methods. The robustness will be checked using skewed distribution. The project will be further extended to design for high speed and advanced technology of 90nm in future.Keywords
Multiplier, Carry Save Reduction, Booth Multiplier, Error Compensation.- Analysis of Data Skipping using Low Transition Switch Registers
Abstract Views :217 |
PDF Views:0
Authors
S. Jayasri
1,
D. Nithya
1
Affiliations
1 Nano Electronics and Integration Division, IRRD Automatons, IN
1 Nano Electronics and Integration Division, IRRD Automatons, IN
Source
ICTACT Journal on Microelectronics, Vol 5, No 4 (2020), Pagination: 850-853Abstract
The emerging scenario in the fields of VLSI testing has its own demand for fault diagnosis in VLSI circuits. If the area and size of the circuit increases the problem of test generation time becoming very tough. Efficient techniques for test generations are essential in order to reduce the test generation time and size. In Existing methods, Low transition Switch Register (LTSR) applies the corresponding repeated patterns of the generated test data. The complication in the LTSR technique exponentially increases power with respect to the circuit size. In case of circuit which has more stuck-at-fault, the LTSR method fails to provide suitable fault coverage and low power consumption. The proposed test data skipping scheme using Reconfigurable Johnson counter reduces the test data volume from the multiple test pattern and reduces switching transitions by skipping the test sequence mostly between the consecutive test sequences. The RJC based Test data skipping scheme has additional circuit which consists of various counters, Bit skipping circuit and logic gates. Memory unit consists of the whole test sequence then these test sequences are fed to RJC and Switching Transition counter. The consecutive test sequence are eliminated or skipped by comparing those counters and the state analysis of FSM. The proposed test data skipping scheme circuit is developed to achieve minimum test patterns and reduced scan power by skipping long scan chain switching activities. This present work with the above mentioned issues for LTSR and existing in VLSI circuits is to examine all detectable faults with proposed circuit. The Efficiency of such system is tested by Xilinx and ISE tools to generate test patterns to achieve high fault coverage with low power consumption over the conventional systems.Keywords
LTSR, Test Data Skipping Algorithm, Reconfigurable Johnson counter, ATPG.- Analysis of Stacked Antenna in Satellite Application
Abstract Views :188 |
PDF Views:0
Authors
S. Jayasri
1,
A. Daniel
2
Affiliations
1 Department of Nanoelectronics and Integration Division, IRRD Automatons, IN
2 School of Computing Science and Engineering, Galgotias University, IN
1 Department of Nanoelectronics and Integration Division, IRRD Automatons, IN
2 School of Computing Science and Engineering, Galgotias University, IN