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Vinoth, R.
- A Robust Flip-Flop for Industrial Applications
Abstract Views :319 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, R.M.K. Engineering College, IN
1 Department of Electronics and Communication Engineering, R.M.K. Engineering College, IN
Source
ICTACT Journal on Microelectronics, Vol 2, No 1 (2016), Pagination: 188-192Abstract
Flip-flops are the basic building blocks of any sequential circuits which occupy the maximum area in a circuit. So the robustness of the system greatly depends on the reliable operation of the flip-flop. In this work the PowerPC 603 flip-flop is simulated and analyzed to measure its reliability against variations in supply voltage and temperature. Performance analysis has been made by having Power, Delay and PDP as Figures of Merit. The acquired simulation results revealed the different sources of power consumption in different scenarios. The simulated results using finer technologies with Synopsys HSPICE prove that PowerPC 603 is a resilient flip-flop for all corners.Keywords
PowerPC 603, Flip-Flop, Low Power.
- Design and Implementation of High Speed Latched Comparator Using gm/Id Sizing Method
Abstract Views :239 |
PDF Views:1
Authors
R. Vinoth
1,
S. Ramasamy
2
Affiliations
1 Automotive Infotainment Systems, Microchip Technology Pvt. Ltd., IN
2 School of Electrical Engineering and Computing, Addis Ababa Science and Technology University, ET
1 Automotive Infotainment Systems, Microchip Technology Pvt. Ltd., IN
2 School of Electrical Engineering and Computing, Addis Ababa Science and Technology University, ET
Source
ICTACT Journal on Microelectronics, Vol 2, No 4 (2017), Pagination: 300-304Abstract
Design of an analog circuit depends on several factors such as design methodology, good modeling and technology characterization. This work focuses on designing a high speed (1.6GHz) latched comparator with low power consumption suitable for ADCs in SoC applications. The latched comparator is designed with StrongArm latch as the primary decision and amplification stage followed by a latching element to drive the output load. The StrongArm latch is a proven circuit topology suitable for all seasons. The zero static power consumption of StrongArm latch is exploited to design a low power comparator. The output latch is used to hold the previous output value during the tracking time of the comparator. The designed comparator achieves zero setup time at a clock frequency of 1.6GHz and produces digital output with a maximum delay of 180ps.The comparator is implemented with SAED 32nm technology libraries. The performance has been analyzed using HSPICE simulator.Keywords
Latched Comparator, Strong Arm Latch, High Speed, Low Power.References
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