ICTACT Journal on Microelectronics

R. Manoj Kumar ¹, P. V. Sridevi ¹

Affiliations
1 Department of Electronics and Communication Engineering, Andhra University of College of Engineering, IN

Abstract

6T SRAM cell has fast differential sensing and offers high density but read-write conflict exists which puts restrictions on the sizing of the devices. This degrades the stability in read mode with the declining supply voltage. To eliminate it, 8T SRAM cell incorporates decoupled read port to enhance the read stability. But it suffers from the data-dependent leakage which deteriorates the Read Bit Line swing. So, the data-independent and low leakage power is necessary to enhance the read sensing margin. To achieve the above, a new 10T SRAM cell is proposed which incorporates data independency and low leakage power. At the worst process corner FF, there is a reduction of 13.7%, 27.7% in leakage power of P10T SRAM cell compared to 10T1 SRAM and 10T2 SRAM cells at 0.9V while holding 0. The variation of supply voltage and the temperature has been studied on the leakage power. All the designs were implemented in 45nm technology and Post Layout simulation has been carried in Cadence Virtuoso.

Keywords

Leakage Power, Data Independent Leakage, Process Corner, Stability.

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R. Manoj Kumar ¹, P. V. Sridevi ¹

Affiliations
1 Department of Electronics and Communication Engineering, Andhra University College of Engineering, IN

Abstract

SRAM used for the FPGA, requires higher stability and low power consumption. 8T SRAM cell has degraded write stability with the decreasing supply voltages. 10T SRAM cell has higher write stability because of the cut-off switch employed in the pull-up path in one of the inverters. The design of SRAM array with low power consumption and higher stability is of major importance. So, 1Kb SRAM array using 8T and 10T SRAM cells has been designed and compared for different design metrics. Write 0 and Write 1 power is lower by 1.98×, 3.52× in 10T SRAM Array than 8T SRAM Array at 0.9VDD, SS corner. Due to the usage of High-Vth transistors in 10T SRAM cell, the Read power is lower by 1.6× than 8T SRAM Array for 0.9V VDD at SS Corner. The leakage power while holding 0 is lower by 1.13× in 10T SRAM array than 8T SRAM array at FF corner at 0.9V VDD. The design metrics are evaluated for a wide range of supply voltage. The designs are implemented in Cadence Virtuoso in 45nm Technology node.

Keywords

SRAM Peripherals, Power, Delay.

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