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Saranya, P. M.
- Design of Standard Cell ASIC's Using Self Gated Resonant Clocked Flip Flop
Abstract Views :218 |
PDF Views:6
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 2 (2017), Pagination: 385-388Abstract
Efforts to reduce power consumption of digital CMOS circuits have been in progress for nearly three decades. As a result, a number of well understood and proven techniques for reducing dynamic and leakage power have been developed. These methods are implemented thoroughly in the circuit level. So we have to shift our concentration towards high level circuits. One of the example for high level circuit is a standard cell Application Specific Integrated Circuit (ASIC). Reducing the power and delay of standard cell ASIC can improve the performance of the system designed using these. A major contributor to the total power in modern microprocessors is the clock distribution network, which can dissipate as much as 70% of the total power for high performance applications. Self-gated resonant-clocked flip-flop optimized for power efficiency and signal integrity achieves reduced dynamic power dissipation, in addition to the negative setup time, which makes the design more tolerant to the clock skew. This feature also reduces the D-Q delay, thus improving the timing performance of the flip-flop. The advantages of the Self gated resonant clocked flip-flop are implemented on standard cell ASICs. Cadence EDA tools and the 180nm process technology files have been used to substantiate the merits of the proposed design.Keywords
Application Specific Integrated Circuit (ASIC), SGR Clocked Flip-Flop.
References
- N. Kulkarni, J. Yang, J-S. Seo and S. Vrudhula, “Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 9, pp. 2873-2886, 2016.
- J.J.D. Jawahar, S.M.S. Murthy and K.B.V. Somasundaram, “Self-Gated Resonant-Clocked Flip-Flop Optimised for Power Efficiency and Signal Integrity”, IET Circuits, Devices & Systems, Vol. 10, No. 2, pp. 94-103, 2016.
- P.R. Panda, B.V.N. Silpa, A. Shrivastava and K. Gummidipudi, “Power-Efficient System Design”, Springer Science and Business Media, 2010.
- B. Nikolic, V.G. Oklobdzija, V. Stojanovic, W. Jia, J.K.S. Chiu and M.M.T. Leung, “Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 6, pp. 876-884, 2000.
- B. Voss and M. Glesner. “A low Power Sinusoidal Clock”, Proceedings of IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 108-111, 2001.
- W.C. Athas, L.J. Svensson, J.G. Koller, N. Tzartzanis, and E.Y.C. Chou, “Low-Power Digital Systems based on Adiabatic-Switching Principles”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 2, No. 4, pp. 398-407, 1994.
- H. Mahmoodi, V. Tirumalashetty, M. Cooke and K. Roy, “Ultra Low-Power Clocking Scheme using Energy Recovery and Clock Gating”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 1, pp. 33-44, 2009.
- V. Tirumalashetty and H. Mahmoodi, “Clock Gating and Negative Edge Triggering for Energy Recovery Clock”, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 1141-1144, 2007.
- V.S. Sathe, J.Y. Chueh and M.C. Papaefthymiou, “Energy-Efficient GHz-Class Charge-Recovery Logic”, IEEE Journal of Solid-State Circuits, Vol. 42, No. 1, pp. 38-47, 2007.
- M. Cooke, H.M. Meimand and K. Roy, “Energy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications”, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, pp. 54-59, 2003.
- J.M. Rabaey, “Digital Integrated Circuits: A Design Perspective”, Prentice Hall, 1996.
- Design Of High Performance Double Tail Comparator
Abstract Views :156 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 3 (2017), Pagination: 437-440Abstract
Comparator is an important building blocks used in analog-to-digital converters. Its function is to compare two analog inputs and delivers a logic value at the output. In this project an analysis on the delay of various dynamic comparators are presented. Based on the analysis a new dynamic comparator is designed for fast operations. Positive feedback mechanism is used to regenerate the analog input signal into full scale digital level. This design is a modification of conventional double-tail comparator. Addition of a few transistors to the conventional double-tail comparator results in remarkably reduced time delay. Kick-back noise of this comparator is also reduced. The large voltage variations in the internal nodes are coupled to the input nodes, which will disturb the input nodes-this is called kick-back noise. This is reduced by inserting switches before the input transistors of comparator. The performance of conventional comparator and proposed comparator circuits are evaluated based on Cadence 180nm CMOS process models.Keywords
Analog To Digital Converter (ADC), Double Tail Comparator, Kick Back Noise.References
- Samanesh Babayan-Mashhadi and Reza Lotfi, “Analysis and Design of a Low-Voltage-Power Double-Tail Comparator”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 2, pp. 343-352, 2014.
- D. Shinkel, E. Mensink, E. Klumperink, E. Van Tuiji and B. Nauta, “A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time”, Proceedings of IEEE International Solid-State Circuits Conference, pp. 314-315, 2007.
- Pedro M. Figueiredo and Joao C. Vital, “Kick-back Noise Reduction Techniques for CMOS Latched Comparators”, IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 53, No. 7, pp. 541-545, 2006.
- B. Goll and H. Zimmermann, “A 0.12 μm CMOS Comparator requiring 0.5V at 600MHz and 1.5V at 6GHz”, Proceedings of IEEE International Solid-State Circuits Conference, pp. 316-317, 2007.
- A. Mesgarani, M.N. Alam, F.Z. Nelson and S.U. Ay, “Supply Boosting Techniques for Designing very Low-Voltage Mixed-Signal Circuits in Standard CMOS”, Proceedings of 53rd IEEE International Midwest Symposium on Circuits and Systems, pp. 893-896, 2010.
- B. Goll and H. Zimmermann, “A 65nm CMOS Comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V”, Proceedings of IEEE International Solid-State Circuits Conference, pp. 328-329, 2009.
- B. Goll and H. Zimmermann, “A Comparator with Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65V”, IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 56, No. 11, pp. 810-814, 2009.
- Jun He, Sanyi Zhan, Degang Chen and Randall L. Geiger, “Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparatos”, IEEE Transactions on Circuits and Systems-I: Regular papers, Vol. 56, No. 5, pp. 911-919, 2009
- P. Amaral, J. Goes, N. Paulino and A. Steiger-Garcao, “An Improved Low-Voltage Low-Power CMOS Comparator to be used in High-Speed Pipeline ADCs”, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 141-144, 2002.
- Y. Wang and B. Razavi, “An 8-bit 150-MHz CMOS A/D Converter”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, pp. 308-317, 2000.
- L.Y. Nathawad, R. Urata, B.A. Wooley and D.A.B. Miller, “A 40-GHz-Bandwidth, 4-bit, Time-Interleaved A/D Converter using Photoconductive Sampling”, IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, pp. 2021-2030, 2000.
- Ata Khorami and Mohammad Sharifkhani, “A High-Speed Method of Dynamic Comparators for SAR Analog to Digital Converters”, Proceedings of IEEE 59th International Midwest Symposium on Circuits and Systems, pp. 1-4, 2016.